Port Supervision Circuit for Background Parity Integrity Checks
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Solution Overview
Problem
Integrated circuits in harsh environments face data integrity issues due to disturbances and latent defects, which existing solutions like redundancy and parity monitoring are costly and inefficient, especially when dealing with 'stuck at' conditions on control signals.
Innovation Solution
A port supervising device that operates in a background loop to monitor and check data integrity across a range of port addresses, generating error signals for inconsistencies and reducing the load on the central processing unit by performing parity checks independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant components are used to supervise port data integrity, then reliability is improved, but device complexity and silicon area increase significantly
Solution Approach 1:
The invention extracts the supervision function from the central processing unit and implements it as an independent port supervising device. This separate entity monitors port data integrity through parity checks without involving the CPU, thereby improving reliability while avoiding the complexity and area overhead of full redundancy schemes.
Solution Approach 2:
The port supervising device acts as an intermediary between the CPU and peripheral devices. It intercepts and verifies data transmitted through ports, generating error signals when data integrity issues are detected. This intermediary approach provides supervision without requiring redundant components throughout the system.
2Reliability
If parity bits are added to monitor data integrity, then reliability is improved, but device complexity increases
Solution Approach 1:
The port supervising device performs self-service by autonomously executing parity checks on port data without requiring complex verification units or CPU intervention. The device independently generates error signals when data integrity violations are detected, simplifying the overall system architecture while maintaining high reliability.
3Reliability
If the CPU performs frequent parity checks on all ports, then data integrity monitoring is improved, but productivity decreases due to CPU load
Solution Approach 1:
The invention extracts the parity check functionality from the CPU and implements it in a dedicated port supervising device. This allows continuous monitoring of port data integrity without burdening the CPU, thereby maintaining both high reliability and CPU productivity. The supervising device operates independently, performing verification tasks that would otherwise consume valuable CPU resources.
4Reliability
If comprehensive port supervision is implemented, then reliability is improved, but silicon area increases
Solution Approach 1:
The port supervising device serves as an intermediary that provides comprehensive supervision with minimal silicon area overhead. By centralizing the verification function in a single dedicated device rather than distributing it across multiple components, the invention achieves system-wide monitoring while minimizing the total area consumed by verification infrastructure.
Data Source
AI summary
A device for supervising ports of an integrated circuit is arranged for exchanging information with a central processing unit of an integrated circuit and for communicating with ports of the integrated circuit. The device comprises address decoding means, access control means, and parity controlling means. The device for supervising ports comprises read-back information means arranged for receiving input from the port and for passing that input to the parity control means and in that the address decoding means, the access control means, the read-back information means and the parity controlling means are arranged to be operative in a background loop wherein a range of port addresses is monitored. The read-back information means reads data and one or more parity bits stored on ports with an address in the range and the parity controlling means performs a parity check on the one or more parity bits stored on the ports.