Attribute-Point Timing Verification for Ported ASIC Constraints
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Solution Overview
Problem
Design porting of application-specific integrated circuits (ASIC) and System on Chips (SoC) across different technology nodes faces challenges in validating timing constraints, leading to potential mismatches and performance issues due to differences in process technologies, which can result in incomplete pin-to-pin compatibility and require extensive engineering tuning.
Innovation Solution
The attribute-point-based timing constraint verification methodology extracts and compares valid timing paths and critical attributes between a golden and target circuit design, identifying mismatches and allowing for design updates to ensure compatibility, using static timing analysis (STA) databases and point-by-point comparisons to correct mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design porting is performed across different technology nodes, then design time is reduced through re-use of circuit blocks, but timing constraint validation becomes challenging due to process technology differences
Solution Approach 1:
The patent segments the timing validation process into discrete attribute-point comparisons. Instead of performing comprehensive timing analysis on entire circuits, the method extracts and compares specific timing attributes (arrival time, required time, slack) at critical points in the design hierarchy. This segmentation enables efficient validation of ported designs by focusing only on relevant timing characteristics rather than analyzing all timing paths.
Solution Approach 2:
The patent introduces an intermediary validation layer between design porting and full timing analysis. The attribute-point comparison method acts as a mediator that quickly assesses timing compatibility before committing to extensive timing verification. This intermediary step identifies potential timing issues early, allowing engineers to address problems before they propagate through the full design validation process.
2Reliability
If comprehensive timing re-verification is performed on ported designs, then performance goals are ensured, but design iteration time increases significantly
Solution Approach 1:
The patent performs preliminary timing attribute extraction and comparison before full timing verification. By pre-identifying critical timing attributes and comparing them at the attribute-point level, the method prepares validation data in advance, enabling faster iteration cycles. This preliminary action filters out designs that clearly meet timing requirements without requiring exhaustive analysis.
Solution Approach 2:
The patent applies partial timing verification by focusing on critical attribute-points rather than exhaustive timing analysis. The method extracts and compares only the most relevant timing attributes at key design points, performing sufficient validation to ensure performance goals are met without the overhead of complete timing verification on all design paths.
3Productivity
If attribute-point-based comparison is used for timing validation, then design iteration time is reduced, but comprehensive timing analysis may be insufficient
Solution Approach 1:
The patent applies local quality by focusing timing validation on specific critical points and attributes rather than uniform analysis across the entire design. The attribute-point comparison method identifies and validates timing characteristics at key locations in the design hierarchy, applying detailed analysis only where needed to ensure performance goals are met while maintaining overall design productivity.
Data Source
AI summary
Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).