Portion Isolation Architecture for Chip Test Yield
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Solution Overview
Problem
Current chip manufacturing technologies face challenges in efficiently isolating and testing partially defective portions of chips, leading to low device yields due to the integration of complex functions and high integration densities, where a defective portion renders the entire chip defective, and existing portion wrapping methods incur hardware overhead and do not optimize logic effectively.
Innovation Solution
A method and system for providing portion isolation design in chip manufacturing that involves retrieving a chip design file, generating pin group files, combining these with portion netlists to form localized wrapper segments, and stitching them into a boundary wrapper chain for insertion into the chip design file, facilitating partial-good portion isolation testing without adding hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional portion wrapping methods are used to isolate portions for testing, then portion isolation testing can be performed, but hardware overhead and congestion increase
Solution Approach 1:
The chip design is segmented into multiple portions with distinct boundaries. Each portion is independently identifiable through the boundary description language, allowing selective testing of individual portions without requiring complex wrapping infrastructure. The segmentation enables the test system to isolate and test only the defective portion rather than requiring wrapper-based isolation of entire functional blocks.
Solution Approach 2:
A boundary description language serves as an intermediary between the physical chip structure and the test system. This language provides a standardized interface for describing portion boundaries and facilitating communication between the test system and chip portions, eliminating the need for hardware wrappers while maintaining isolation testing capability.
2Adaptability or versatility
If high integration density is used to increase chip functionality, then more functions can be integrated, but device yield decreases due to higher probability of defects
Solution Approach 1:
The chip is divided into multiple independent portions that can be individually tested and evaluated. This segmentation allows the test system to identify which specific portions are defective and which are functional, enabling the chip to be classified as partially good rather than completely defective, thus improving overall yield despite high integration density.
Solution Approach 2:
Different portions of the chip can have different quality assessments based on their individual test results. The boundary description language enables precise localization of defects to specific portions, allowing the system to apply different quality criteria to different regions of the chip rather than applying a uniform pass/fail criterion to the entire device.
3Ease of operation
If traditional testing methods are used without portion isolation, then testing is simpler, but the ability to identify partially good portions is lost
Solution Approach 1:
The boundary description language acts as an intermediary that adds precise measurement capability without significantly complicating the testing process. It provides a standardized format for describing portion boundaries that can be easily parsed and processed by test systems, enabling accurate defect localization while maintaining operational simplicity through automated boundary interpretation.
Data Source
AI summary
Embodiments include methods, and processing system, and computer program products providing portion isolation design to a chip design to facilitate partial-good portion isolation test of the chip. Aspects include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test.