Portioned Memory Erase for Read Window Budget Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in maintaining read window budget (RWB) and endurance due to threshold voltage shifts in memory cells caused by prolonged idle periods between erase and write operations, leading to decreased separation between voltage values representing distinct logic states.
Innovation Solution
Performing a partial erase operation in the background, consisting of a first subset of erase cycles before a write command and a second subset in response to the command, to mitigate threshold voltage shifts and maintain RWB while enhancing endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complete erase operation is performed before every write operation, then the read window budget is maintained, but the endurance of memory cells deteriorates due to excessive erase cycles
Solution Approach 1:
The patent applies partial erase action by performing only a subset of the required erase cycles during background operations, rather than completing the full erase sequence. This partial erasure is sufficient to mitigate threshold voltage shifts without requiring the complete erase operation, thereby reducing wear on memory cells while maintaining adequate read window budget.
Solution Approach 2:
The patent performs preliminary erase cycles during background operations before the actual write operation occurs. By advancing part of the erase process beforehand, the system reduces the threshold voltage shift that would otherwise accumulate during idle periods, ensuring better read window budget without requiring a full erase immediately before writing.
2Duration of action of stationary object
If erase operations are delayed to improve endurance, then memory cell wear is reduced, but threshold voltage shifts increase causing degraded read window budget
Solution Approach 1:
The system performs preliminary erase cycles during background operations before write operations occur. This advance action mitigates threshold voltage shifts that would otherwise accumulate during idle periods, ensuring adequate read window budget is maintained without requiring immediate full erase operations that would reduce endurance.
Solution Approach 2:
The patent implements periodic erase cycles during background operations rather than continuous or immediate erasure. By distributing erase cycles periodically over time during idle periods, the system effectively manages threshold voltage shifts while reducing the intensity and frequency of full erase operations, thereby preserving memory cell endurance.
3Reliability
If more erase cycles are performed during background operations, then threshold voltage shifts are better mitigated, but the complexity of erase management increases
Solution Approach 1:
The patent performs a subset of the total required erase cycles during background operations, rather than completing all erase cycles immediately. This partial execution approach mitigates threshold voltage shifts without requiring complex coordination of full erase sequences, simplifying the management logic while achieving the desired voltage stabilization.
Data Source
AI summary
Methods, systems, and devices for an erase operation for a memory system are described. The memory system may perform, on a block of memory cells, a first portion of an erase operation. After performing the first portion of the erase operation, the memory system may receive a write command to write data to the block of memory cells. In response to receiving the write command, the memory system may determine whether a threshold voltage of the block of memory cells satisfies a threshold. In response to determining the that the threshold voltage satisfies the threshold, the memory system may perform a second portion of the erase operation on the block of memory cells. As such, the memory system may write the data to the block of memory cells in response to performing the second portion of the erase operation.