Fixed-Length Posit Floating-Point Encoding for Simpler Arithmetic Circuits

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Solution Overview

Problem

Operation devices that support Posit floating-point numbers are larger in circuit scale and have higher power consumption compared to those supporting typical floating-point formats like IEEE 754.

Innovation Solution

A storage medium and operation device utilizing a floating-point number data structure with a fixed combined code length, where the exponent part is encoded using variable-length coding, allowing for a fixed correspondence between digit and bit positions, reducing the need for complex shift processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If Posit floating-point format with variable-length exponent coding is used, then dynamic range and numerical accuracy are improved, but circuit scale and power consumption increase significantly

Engineering Contradiction:
Improvenumerical accuracyVSAvoidcircuit scale
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the floating-point number into three distinct parts: sign part, exponent part, and significand part. This segmentation allows each part to be processed independently, simplifying the circuit design. The variable-length exponent is handled through dedicated decoding logic that converts it to a fixed-length format, enabling modular processing and reducing overall circuit complexity while maintaining the benefits of variable-length encoding for improved numerical accuracy.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If Posit floating-point format with variable-length exponent coding is used, then dynamic range and numerical accuracy are improved, but power consumption increases significantly

Engineering Contradiction:
Improvenumerical accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent employs dynamic conversion of the variable-length exponent to a fixed-length exponent format during processing. This dynamic approach allows the system to adapt to different exponent lengths without requiring dedicated hardware for each possible length, thereby reducing power consumption. The conversion logic dynamically adjusts the processing based on the actual exponent length, maintaining numerical accuracy while minimizing energy usage compared to static designs that must accommodate the maximum possible exponent length.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If variable-length coding is used for the exponent part, then larger dynamic range is achieved, but complex shift processes are required

Engineering Contradiction:
Improvedynamic rangeVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a fixed-length exponent part as an intermediary between the variable-length exponent and the significand. This intermediary serves as a bridge that translates the variable-length exponent into a standardized fixed-length format, eliminating the need for complex shift processes. The fixed-length exponent acts as a mediator that simplifies the interaction between different parts of the floating-point number, maintaining the large dynamic range benefits of variable-length encoding while reducing circuit complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12210851B2Storage medium and operation device handling an alternative floating-point format
Publication Date: 2025.01.28 KK TOSHIBA
  • US12210851B2 patent drawing
  • US12210851B2 patent drawing
  • US12210851B2 patent drawing

AI summary

A structure of floating-point number data stored in a storage medium according to an embodiment is provided with a first partial code obtained by encoding all or part of an exponent of a floating-point number using variable-length coding, and a second partial code including a significand of the floating-point number. The length of the combined code of the first partial code and the second partial code is fixed, and the end bit of the first partial code and the least significant hit of the second partial code are adjacent to each other.