Posit Tensor Processing for High Precision Computing

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Solution Overview

Problem

Current computing systems face limitations in memory resources, leading to inefficiencies in performing calculations due to the finite storage capacity for operands, particularly when using floating-point formats, which can result in reduced accuracy, increased processing time, and higher power consumption.

Innovation Solution

The implementation of posit tensor processing using a processing unit with a multiplier-accumulator block configured to perform operations on universal number or posit bit strings organized in matrices or tensors, allowing for higher precision, dynamic range, and accuracy, and reducing the need for additional memory and processing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If floating-point formats are used for storage, then memory capacity is sufficient, but calculation accuracy and processing speed are reduced

Engineering Contradiction:
Improvecalculation accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent changes the numerical representation parameter from floating-point format to posit format. Posit format uses a simplified representation with a sign bit, exponent bits, and fraction bits, eliminating the need for hidden bits and normalization operations. This parameter change enables higher precision and faster processing by reducing the complexity of number representation and arithmetic operations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the traditional floating-point arithmetic mechanism with a posit-based arithmetic mechanism. The posit format substitutes the complex floating-point normalization and rounding mechanisms with simpler operations that directly manipulate the posit representation, thereby improving both accuracy and processing speed in neural network computations.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Quantity of substance

If more memory resources are allocated for operands, then storage capacity increases, but processing time and power consumption increase

Engineering Contradiction:
Improvememory capacityVSAvoidprocessing time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent changes the data representation parameter to posit format, which requires fewer bits than floating-point format to achieve the same precision. This parameter change reduces the memory footprint of operands while maintaining or improving calculation accuracy, thereby reducing the total memory capacity needed and the associated processing time and power consumption.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If traditional floating-point systems are used, then compatibility is maintained, but computational efficiency and accuracy are reduced

Engineering Contradiction:
Improvesystem compatibilityVSAvoidcomputational efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces posit format as an intermediary representation that bridges traditional floating-point systems and high-performance computation. The posit format can be converted from and to floating-point representations, enabling compatibility with existing systems while providing the computational efficiency and accuracy benefits of optimized arithmetic operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11928442B2Posit tensor processing
Publication Date: 2024.03.12 MICRON TECHNOLOGY INC
  • US11928442B2 patent drawing
  • US11928442B2 patent drawing
  • US11928442B2 patent drawing

AI summary

A method related to posit tensor processing can include receiving, by a plurality of multiply-accumulator (MAC) units coupled to one another, a plurality of universal number (unum) or posit bit strings organized in a matrix and to be used as operands in a plurality of respective recursive operations performed using the plurality of MAC units and performing, using the MAC units, the plurality of respective recursive operations. Iterations of the respective recursive operations are performed using at least one bit string that is a same bit string as was used in a preceding iteration of the respective recursive operations. The method can further include prior to receiving the plurality of unum or posit bit strings, performing an operation to organize the plurality of unum or posit bit strings to achieve a threshold bandwidth ratio, a threshold latency, or both during performance of the plurality of respective recursive operations.