Memory Channel Precharge Using Position-Based Row-Circuit Control

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Solution Overview

Problem

Existing memory technologies face inefficiencies in channel precharge operations during programming, leading to issues such as data loss and increased power consumption due to continuous power supply requirements for volatile memories and slow data processing in non-volatile memories.

Innovation Solution

A memory system with a cell string configuration that includes select transistors and a row circuit, which performs differential discharge and precharge operations based on the position of cell transistors within the string to optimize channel potential and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If continuous power is supplied to maintain stored data in volatile memory, then data retention is improved, but power consumption increases

Engineering Contradiction:
Improvedata retentionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic channel precharge operations during programming instead of continuous power supply. The row circuit periodically discharges and recharges select lines and word lines based on programming progress, maintaining data retention while reducing overall power consumption by eliminating continuous power requirements.

Inventive Principle:
Principle #19Periodic action

2Reliability

If channel precharge is performed during programming, then data loss is reduced, but programming time increases

Engineering Contradiction:
Improvedata loss preventionVSAvoidprogramming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs channel precharge operations in advance and between programming steps. The row circuit discharges select lines and word lines before programming operations and recharges them as needed, preventing data loss from channel potential drops without significantly extending total programming time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically adjusts the timing and duration of precharge operations based on programming progress. The row circuit monitors programming status and performs differential discharge operations - discharging more slowly for cell transistors farther from the second select transistor - optimizing the balance between data loss prevention and programming speed.

Inventive Principle:
Principle #15Dynamics

3Speed

If select lines and word lines are discharged quickly, then programming speed is improved, but channel potential stability deteriorates

Engineering Contradiction:
Improveprogramming speedVSAvoidchannel potential stability
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The patent applies different discharge rates to different parts of the cell string based on position. The row circuit discharges select lines and word lines more slowly for cell transistors located farther from the second select transistor, maintaining channel potential stability in regions more susceptible to potential drops while allowing faster discharge elsewhere to maintain programming speed.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12406740B2Memory configured to perform a channel precharge operation and method of operating the memory
Publication Date: 2025.09.02 SK HYNIX INC
  • US12406740B2 patent drawing
  • US12406740B2 patent drawing
  • US12406740B2 patent drawing

AI summary

A memory includes a cell string including a first select transistor, cell transistors, and a second select transistor and a row circuit configured to drive a first select line for controlling the first select transistor, a second select line for controlling the second select transistor and word lines for controlling the cell transistors. The row circuit differently performs a discharge operation of the first select line according to a position in the cell string of a program target cell transistor.