Positive Feedback LOS Circuit for Fast USB Signal Detection

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Solution Overview

Problem

Existing loss of signal (LOS) detectors in USB and eUSB2 systems have slow response times, often requiring signal filtering that can lead to false detection triggers and increased circuit size, making them incompatible with fast response and minimum propagation delay requirements.

Innovation Solution

A multi-stage switchable positive feedback differential glitch suppressor circuit that uses comparators and positive feedback circuits to determine the magnitude of differential signal lines, eliminating the need for signal filtering in the output path and reducing non-overlapping regions to achieve fast LOS detection within 2 unit intervals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If signal filtering is applied in existing LOS detectors, then false detection triggers are reduced, but response time increases and circuit size increases

Engineering Contradiction:
Improvedetection accuracyVSAvoidresponse time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a positive feedback mechanism where the output of the differential comparator is fed back to its input through a feedback network. This positive feedback creates a latch effect that maintains the output state once a threshold is crossed, eliminating the need for external signal filtering while ensuring stable detection and preventing false triggers.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent employs dynamic switching of feedback paths based on the detection state. When signal levels indicate a loss condition, the feedback network dynamically changes configuration to maintain the detected state, allowing the circuit to adapt its behavior based on real-time signal conditions without requiring slow filtering operations.

Inventive Principle:
Principle #15Dynamics

2Reliability

If signal filtering is applied in existing LOS detectors, then false detection triggers are reduced, but circuit size increases

Engineering Contradiction:
Improvedetection accuracyVSAvoidcircuit size
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the filtering function with the comparison and detection functions into a single integrated circuit block. The feedback network performs both signal level comparison and false trigger prevention simultaneously, eliminating the need for separate filtering components and reducing overall circuit complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The differential comparator circuit serves its own filtering needs through the positive feedback mechanism. The feedback network automatically suppresses false triggers by maintaining the output state once a valid detection is made, making the circuit self-sufficient without requiring external filtering components.

Inventive Principle:
Principle #25Self-service

3Speed

If fast response LOS detection is implemented, then detection speed improves, but susceptibility to false triggers increases

Engineering Contradiction:
Improvedetection speedVSAvoidfalse trigger rate
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent prepares the feedback network in advance to immediately latch the output state when a threshold crossing occurs. This preliminary configuration of the feedback path ensures that once a valid loss condition is detected, the circuit rapidly stabilizes to the correct state without oscillation or false transitions, achieving both speed and reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10763841B2Loss of signal detection circuit
Publication Date: 2020.09.01 TEXAS INSTRUMENTS INC
  • US10763841B2 patent drawing
  • US10763841B2 patent drawing
  • US10763841B2 patent drawing

AI summary

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.