Positive-Logic FET Switch Stack With Selectable DC Blocking
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Solution Overview
Problem
Existing RF switch circuits using FET stacks face challenges such as requiring negative bias voltages, high insertion loss, and vulnerability to high voltage RF signals, which limits their performance and reliability, especially in applications with stringent power and area constraints.
Innovation Solution
A positive-logic FET switch stack configuration that eliminates the need for negative bias voltages, utilizing end-cap FETs for DC blocking and resistive signal paths, along with series-connected bias and drain-source resistor ladders, and optional AC coupling modules to enhance high voltage handling and reduce IC area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If negative bias voltages are used in FET switch stacks, then the switches can be controlled to block or conduct RF signals, but power consumption increases due to negative charge pumps
Solution Approach 1:
The patent inverts the conventional biasing approach by using positive bias voltages instead of negative bias voltages to control the FET switches. This inversion eliminates the need for negative charge pumps and their associated power consumption, while still achieving effective switch control through the complementary series-shunt configuration.
Solution Approach 2:
The patent extracts and removes the negative charge pump circuitry from the system by eliminating the need for negative bias voltages. By using positive bias voltages and configuring the FETs appropriately, the harmful power-consuming component (negative charge pump) is completely taken out while maintaining switch functionality.
2Reliability
If negative charge pumps and large DC blocking capacitors are used, then FET switches can be controlled, but IC area consumption increases
Solution Approach 1:
The patent extracts and eliminates large DC blocking capacitors from the circuit by using FETs configured to provide inherent DC blocking through their off-state capacitance. This removal of large external capacitors significantly reduces IC area consumption while maintaining the necessary DC blocking functionality for RF signal control.
Solution Approach 2:
The FETs in the patent serve multiple functions simultaneously: they act as switches for RF signal control, provide DC blocking through their off-state capacitance, and eliminate the need for separate negative charge pumps. This multi-functionality reduces the overall component count and IC area required.
3Reliability
If negative charge pumps and large DC blocking capacitors are used, then FET switches can be controlled, but ESD sensitivity increases
Solution Approach 1:
The patent extracts and removes the vulnerable negative charge pump and large DC blocking capacitor circuits that are sensitive to ESD events. By using a simplified positive-logic FET switch configuration, the system eliminates these harmful ESD-sensitive components while maintaining switch control capability.
4Strength
If FET stacks are used to withstand high voltages, then voltage handling capability improves, but switching speed decreases
Solution Approach 1:
The patent segments the high-voltage handling function across multiple FETs in a series stack configuration, where each FET handles a portion of the total voltage. This segmentation allows the system to withstand high voltages while maintaining faster switching speeds compared to using a single high-voltage FET, as each individual FET in the stack can switch more rapidly.
Data Source
AI summary
A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.