Positive-Logic FET Switch Stack for High-Voltage RF Handling
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Solution Overview
Problem
Existing FET-based RF switch circuits face challenges in handling high voltage RF signals without requiring negative bias voltages and consuming large IC areas, as they often rely on terminal capacitors that increase insertion loss.
Innovation Solution
A FET-based RF switch stack that uses a stack of positive-logic FETs series-coupled with end-cap FETs, where switch circuits are employed between the RF signal source and the gate of end-cap FETs to control voltage swings, eliminating the need for terminal capacitors and allowing high voltage RF signal handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If terminal capacitors are used in FET-based RF switch circuits to handle high voltage RF signals, then voltage handling capability is improved, but insertion loss increases and IC area consumption increases
Solution Approach 1:
The patent removes terminal capacitors from the RF switch circuit entirely. Instead of using capacitors to handle high voltage, the invention employs a stack of FETs with carefully engineered gate structures and biasing schemes that inherently withstand high voltage RF signals without requiring external capacitive elements, thereby eliminating the associated insertion loss and area overhead.
Solution Approach 2:
The patent modifies the electrical parameters of the FETs themselves, specifically optimizing gate length, width, and doping profiles to enhance voltage handling capability. By changing these device parameters rather than adding passive components, the circuit achieves high voltage tolerance without the penalties of terminal capacitors.
2Strength
If terminal capacitors are used in FET-based RF switch circuits to handle high voltage RF signals, then voltage handling capability is improved, but IC area consumption increases
Solution Approach 1:
The patent removes terminal capacitors from the RF switch circuit entirely. Instead of using capacitors to handle high voltage, the invention employs a stack of FETs with carefully engineered gate structures and biasing schemes that inherently withstand high voltage RF signals without requiring external capacitive elements, thereby eliminating the associated insertion loss and area overhead.
Solution Approach 2:
The patent modifies the electrical parameters of the FETs themselves, specifically optimizing gate length, width, and doping profiles to enhance voltage handling capability. By changing these device parameters rather than adding passive components, the circuit achieves high voltage tolerance without the penalties of terminal capacitors.
3Ease of operation
If negative bias voltages are used in FET-based RF switch circuits, then switching control is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The patent inverts the conventional biasing approach by using positive bias voltages instead of negative bias voltages to control the FET switching. This inversion simplifies the biasing circuitry, eliminates the need for negative voltage generation circuits, and reduces overall system complexity while maintaining effective switching control.
Solution Approach 2:
The patent designs the FET stack and gate structures to inherently provide self-biasing characteristics that facilitate switching without requiring external negative voltage supplies. The circuit structure itself generates the necessary bias conditions through its configuration, reducing dependence on complex external biasing networks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables RF switch circuits to handle high voltage RF signals without negative bias voltages and reduces IC area consumption, improving power handling capabilities and minimizing signal compression.
Implementation Method 1
the voltage that a single FET can withstand between drain and source without breaking down is generally limited to a few volts
Implementation Method 2
A common solution is to series stack FETs so that the drain-source voltage across any one FET is less than its drain-source breakdown voltage
Data Source
AI summary
A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative VGS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.