Digitally Tunable Capacitor Using Positive Logic RF Biasing
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Solution Overview
Problem
Conventional methods for generating a negative supply voltage in integrated circuits are impractical or impossible in applications with stringent design constraints, such as low current and power consumption, low noise sensitivity, and small die areas, limiting RF performance and switching speed.
Innovation Solution
A digitally tunable capacitor circuit using a series arrangement of capacitors and FET switches with a resistive network, where non-negative supply voltages are used to enable or disable the switches, eliminating the need for a negative supply voltage and allowing for faster switching times and improved RF linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods for generating negative supply voltage are used, then the capacitor can be tuned, but the current consumption and power consumption increase, and the die area expands
Solution Approach 1:
The patent extracts and eliminates the negative voltage generation circuitry from the system. By using a series arrangement of capacitors with FET switches controlled by positive logic signals, the invention removes the need for negative supply voltage generation, thereby reducing current consumption and power consumption while maintaining capacitor tuning capability.
Solution Approach 2:
The patent changes the control parameter from negative voltage to positive logic signals. By controlling FET switches with positive logic signals applied to their gates, the invention achieves capacitor tuning without requiring negative supply voltage, thus improving power efficiency and reducing current consumption.
2Reliability
If conventional methods for generating negative supply voltage are used, then the capacitor can be tuned, but the switching speed decreases and RF linearity deteriorates
Solution Approach 1:
The patent removes the negative voltage generation circuitry that limited switching speed. By using FET switches controlled by positive logic signals, the invention achieves faster switching times and improved RF linearity while maintaining the capacitor tuning function.
Solution Approach 2:
The patent replaces the conventional voltage-based switching mechanism with a field-effect transistor switching mechanism controlled by positive logic signals. This substitution enables faster switching speeds and improved RF linearity by eliminating the limitations of negative voltage generation and manipulation.
3Reliability
If conventional methods for generating negative supply voltage are used, then the capacitor can be tuned, but the die area increases
Solution Approach 1:
The patent extracts and eliminates the negative voltage generation circuitry from the integrated circuit. By using a series arrangement of capacitors with FET switches controlled by positive logic signals, the invention removes the need for additional circuitry that would consume die area, thereby reducing the overall chip size while maintaining tuning functionality.
4Reliability
If conventional methods for generating negative supply voltage are used, then the capacitor can be tuned, but the noise sensitivity increases
Solution Approach 1:
The patent replaces the conventional negative voltage-based tuning mechanism with a positive logic signal-controlled FET switching mechanism. This substitution reduces noise sensitivity by eliminating the noise-generating negative voltage generation circuitry and using cleaner positive logic signals for control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster switching times, improved RF linearity, and reduced power consumption by using positive logic biasing, which is essential for applications where conventional negative voltage generation is not feasible, enhancing the performance of integrated circuits.
Implementation Method 1
a plurality of FET switches coupled between the first node and the second node... enabling or disabling the FET switches and thereby adjusting the capacitance between the two nodes
Implementation Method 2
each FET switch comprises a gate resistor connecting a FET switch gate to a first supply voltage
Implementation Method 3
the resistive network comprises a plurality of resistive paths connecting a second supply voltage to drains of corresponding FET switches
Implementation Method 4
a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node
Data Source
AI summary
Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.