Positive Netlist Synthesis for Circuit Simulation Compatibility
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Solution Overview
Problem
Existing methods for generating reduced-order models of electronic circuits often result in netlists with non-physical elements, such as negative RLC components or a large number of controlled sources, which are not compatible with many simulation tools, and fail to preserve the block structure and port connectivity, leading to inefficient and inaccurate circuit analysis.
Innovation Solution
A circuit analysis method that uses the PRIMA algorithm for netlist reduction, followed by structure and I/O preservation techniques like SPRIM and IOPOR, and a positive realization method to synthesize a netlist with no controlled sources, ensuring all elements are positive and compatible with simulation software, while maintaining block structure and port connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If model-order reduction algorithms (PRIMA) are applied to reduce netlist size, then computational efficiency is improved, but the resulting netlist contains non-physical elements (negative RLC components, controlled sources) that are not compatible with simulation tools
Solution Approach 1:
The patent applies parameter changes by transforming the reduced-order model parameters through a specific synthesis procedure that converts negative or complex parameters into positive real values. The method modifies the circuit parameters (RLC values) obtained from PRIMA reduction through a systematic transformation that ensures all parameters are positive and physical, making the netlist compatible with simulation tools while preserving the reduced-order computational efficiency.
2Loss of time
If model-order reduction is applied to accelerate simulation, then simulation time is reduced, but the block structure and port connectivity are not preserved
Solution Approach 1:
The patent applies segmentation by dividing the circuit into modular blocks that maintain the original block structure during reduction. The method segments the circuit into manageable portions while preserving the interconnections and port interfaces, allowing the reduced model to maintain both computational efficiency and structural integrity for further design activities.
Solution Approach 2:
The patent uses an intermediary transformation procedure that acts as a mediator between the reduced-order model and the original circuit structure. This intermediary synthesis process ensures that the reduced model preserves port connectivity and block structure by introducing necessary transformation matrices and conversion steps that maintain the structural relationships while achieving order reduction.
3Measurement precision
If controlled sources are introduced to maintain port connectivity, then accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies the taking out principle by extracting and eliminating controlled sources from the circuit model. The method removes the need for controlled sources by using a synthesis approach that directly produces independent sources and passive elements, thereby reducing device complexity while maintaining accuracy through alternative modeling techniques that do not require controlled source elements.
Data Source
AI summary
In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a positive netlist having no controlled current or voltage sources, unstamping the synthesized positive netlist, and simulating the circuit using the unstamped synthesized positive netlist.