Post-Checkstop Hardware Testing for Interfaced Component Evaluation
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Solution Overview
Problem
Existing methods fail to continue testing hardware components after a checkstop event, preventing the evaluation of components not directly involved in the error causing the checkstop.
Innovation Solution
Inject errors into a model of a design under test to cause a checkstop, simulate the model for a number of cycles after the checkstop with suppressed errors, and execute a post-processing script to test the hardware components while ignoring errors caused by the checkstop, allowing continued testing of interfaced hardware components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If testing stops immediately after a checkstop event, then the testing process remains simple and reliable, but the ability to evaluate interfaced hardware components is lost
Solution Approach 1:
The patent segments the testing process into distinct phases: pre-checkstop testing, checkstop detection, post-checkstop suppression period, and post-processing analysis. This segmentation allows the system to maintain reliability during critical phases while extending testing coverage through structured phases, resolving the contradiction between reliability and testing coverage.
Solution Approach 2:
The patent performs preliminary actions by suppressing error injection during the quiesce period after a checkstop event. This preliminary suppression prevents spurious errors from interfering with the evaluation of interfaced components, enabling reliable continued testing without compromising the integrity of the testing process.
2Productivity
If error injection continues after a checkstop, then testing coverage is maintained, but false errors may be generated affecting testing accuracy
Solution Approach 1:
The patent dynamically adjusts the error injection behavior based on the system state. During the quiesce period following a checkstop, error injection is temporarily suspended to prevent false errors. The system then transitions to a post-processing phase where only validated errors are analyzed. This dynamic adaptation maintains testing throughput while ensuring measurement precision by filtering out spurious errors.
Solution Approach 2:
The patent maintains the continuity of useful testing action by implementing a structured post-checkstop process. Instead of completely stopping testing, the system continues with suppressed error injection during the quiesce period, then transitions to post-processing analysis. This continuous approach ensures testing productivity while preventing false errors from compromising accuracy.
3Measurement precision
If the testing process stops after checkstop, then false errors are avoided, but interfaced components cannot be evaluated
Solution Approach 1:
The patent introduces an intermediary post-processing script that acts as a mediator between the checkstop event and the final evaluation. This intermediary component suppresses spurious errors during the quiesce period while still enabling the evaluation of interfaced components through structured post-processing. The mediator thus resolves the contradiction by maintaining measurement precision while preventing complete testing termination.
Solution Approach 2:
The patent changes the parameter of error injection behavior after a checkstop event. By temporarily suppressing error injection during the quiesce period and then transitioning to post-processing analysis, the system maintains measurement precision for error evaluation while continuing to test interfaced components. This parameter change resolves the contradiction between avoiding false errors and maintaining testing time efficiency.
Data Source
AI summary
A computer-implemented method, system, and computer program product for testing hardware in an environment involving a checkstop. Errors are injected into a model of a design under test (DUT), which includes a first hardware component interfaced with a second hardware component, at various states causing an occurrence of a checkstop in the first hardware component. A simulation of the model of the DUT is then performed with the injected errors for a number of cycles after the checkstop based on a quiesce time where the injected errors are suppressed. Furthermore, a post-processing script is executed to test a model of the DUT which ignores the errors of the first hardware component that were identified after the checkstop in the simulation of the model of the DUT. Any non-ignored errors from the execution of the post-processing script are detected and analyzed to determine if the second hardware component failed the test.