Post-CTS Clock Tree Restructuring for Delay Adjustment
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Solution Overview
Problem
Conventional clock tree synthesis (CTS) techniques do not allow for adjustments to clock tree delay placements after the synthesis has completed, making it difficult to reduce delay times or target specific clock sinks, which limits power reduction and design flexibility in integrated circuits.
Innovation Solution
The method involves post-CTS clock tree restructuring by identifying groups of clock sinks and relocating their terminals closer to the clock source, allowing for targeted delay reductions through graphical user interface or automated processes, without regenerating the entire clock tree, and compensating for electrical changes in the clock tree.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CTS techniques are used to generate a clock tree, then the clock tree is initially established, but delay placements cannot be adjusted after synthesis is completed
Solution Approach 1:
The patent segments the clock tree into modular components (clock sinks, terminals, and delay elements) that can be independently identified and repositioned. This segmentation allows selective adjustment of delay placements without regenerating the entire clock tree, thereby improving adaptability while managing complexity through localized modifications.
Solution Approach 2:
The patent introduces dynamic reconfigurability to the clock tree by enabling post-synthesis adjustment of delay placements. The system allows terminals to be moved to different locations and delay values to be modified dynamically, transforming the static clock tree into an adaptable structure that can be optimized after initial synthesis.
2Loss of time
If the entire clock tree is regenerated to reduce delay times, then delay reduction is achieved, but time and resources are excessively consumed
Solution Approach 1:
The patent extracts the delay adjustment functionality from the complete clock tree regeneration process. By identifying and relocating specific terminals and adjusting their delay placements independently, the system achieves delay reduction without the need to regenerate the entire clock tree, thereby conserving time and computational resources.
Solution Approach 2:
The patent applies partial action by performing delay optimization on only the necessary portions of the clock tree rather than regenerating the entire structure. This selective approach reduces the computational overhead and time consumption while still achieving the desired delay reduction for critical paths.
3Adaptability or versatility
If targeted adjustments to specific clock sinks are made, then design flexibility is improved, but the process becomes more complex
Solution Approach 1:
The patent applies local quality by enabling targeted adjustments to specific clock sinks and their associated terminals rather than uniformly modifying the entire clock tree. This localized approach allows design flexibility for specific regions while maintaining the integrity of other parts, managing complexity through focused modifications.
4Loss of energy
If delay placements are fixed after CTS, then the clock tree structure is stable, but power reduction opportunities are lost
Solution Approach 1:
The patent introduces dynamic reconfigurability to the clock tree structure, allowing delay placements to be adjusted after synthesis. This dynamic capability enables power optimization by repositioning terminals and modifying delay values to minimize power consumption, while the structured approach to restructuring maintains overall structural stability.
Data Source
AI summary
Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to update the clock tree. An indication is provided that the updated clock tree has been modified and complies with the target timing offset.