Post-CTS Clock Tree Level Limits for Skew Target Compliance
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Solution Overview
Problem
Conventional EDA software systems face challenges in efficiently modifying post-clock tree synthesis (CTS) clock trees due to the labor-intensive process of adjusting clock sinks, which often leads to design rule violations and increased power consumption, without allowing for automatic adjustments that minimize physical modifications.
Innovation Solution
The system automatically modifies post-CTS clock trees by selectively adding or removing levels and adjusting buffer sizes to meet insertion delay and skew targets, reducing the need for manual intervention and re-synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual adjustment of clock sinks is performed to meet insertion delay and skew targets, then clock tree performance is improved, but the process becomes labor-intensive and time-consuming
Solution Approach 1:
The system automatically identifies clock sinks requiring adjustment and performs the adjustments without manual intervention. The automated process analyzes insertion delay and skew metrics, selects appropriate clock sinks for adjustment, and modifies their parameters to meet targets, eliminating the need for labor-intensive manual adjustment while maintaining precision.
Solution Approach 2:
The system modifies clock sink parameters (such as buffer sizes, insertion delays, and skew values) to achieve target compliance. By automatically changing these parameters based on analysis results, the system resolves the contradiction between achieving precise timing compliance and reducing manual adjustment time.
2Manufacturing precision
If extensive physical modifications are made to clock trees, then insertion delay and skew targets are met, but power consumption increases
Solution Approach 1:
The system automatically analyzes the clock tree and identifies the minimum necessary modifications to meet timing targets. By self-managing the adjustment process and selecting only essential modifications, the system avoids excessive physical changes that would increase power consumption while still achieving compliance with insertion delay and skew targets.
Solution Approach 2:
The system modifies clock sink parameters such as buffer sizes and insertion delays to achieve timing compliance with minimal physical modifications. By carefully controlling parameter changes rather than making extensive modifications, the system meets timing targets while minimizing the increase in power consumption.
3Extent of automation
If automated adjustment is implemented, then manual intervention is reduced, but the complexity of the system increases
Solution Approach 1:
The system performs automated analysis and adjustment of clock sinks without requiring external manual intervention. The automation handles the entire process from analysis to modification, reducing manual effort while managing system complexity through integrated self-service functionality.
Solution Approach 2:
The system combines multiple functions (analysis, identification, selection, and adjustment of clock sinks) into a single automated process. This multi-functionality reduces overall system complexity by integrating what could be separate complex operations into one unified automated system.
4Manufacturing precision
If frequent re-synthesis is performed to optimize clock tree, then design parameters are optimized, but productivity decreases
Solution Approach 1:
The system automatically analyzes clock tree performance and performs targeted adjustments without requiring repeated full re-synthesis operations. This self-service approach maintains design parameter optimization while significantly reducing the time lost to frequent re-synthesis cycles, thereby improving productivity.
Solution Approach 2:
The system makes targeted parameter changes to clock sinks based on analysis results rather than performing extensive re-synthesis. This approach achieves design parameter optimization with minimal re-synthesis, maintaining productivity while still optimizing the clock tree performance.
Data Source
AI summary
Methods and systems for performing post clock tree synthesis of a clock tree. The methods and systems access, from memory, a circuit design comprising a clock tree that interconnects a clock source to a plurality of clock sinks, each clock sink in the plurality of clock sinks having an associated target insertion delay adjustment, the clock tree comprising a restriction on a quantity of levels of components for respectively adding delay to the clock source. The methods and systems identify an individual target insertion delay adjustment associated with an individual clock sink of the plurality of clock sinks and compare the individual target insertion delay adjustment to a threshold value. The methods and systems selectively remove the restriction on the quantity of levels of components to provide the individual target insertion delay adjustment based on comparing the individual target insertion delay adjustment to the threshold value.