Post-ECC CRC Check for DDR Read Retry Reduction
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Solution Overview
Problem
In DDR DRAM systems, existing error correction mechanisms fail to effectively handle link errors, leading to system crashes and performance deterioration due to high retry rates, especially when errors exceed the capability of error correction codes like ECC.
Innovation Solution
Implementing an additional CRC check mechanism, including post-ECC CRC, to determine when to perform read retry operations, thereby reducing the number of retries and improving system performance by differentiating between single-bit and multi-bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read retry operations are performed frequently to handle link errors, then system reliability is improved, but system performance deteriorates due to high retry rates
Solution Approach 1:
The patent applies preliminary action by performing a CRC check on the received data packet before attempting ECC correction. This preliminary verification identifies link errors that cannot be corrected by ECC, allowing the system to avoid unnecessary retry operations and directly report uncorrectable errors, thereby improving performance while maintaining reliability.
Solution Approach 2:
The patent introduces CRC as an intermediary mechanism between the received data packet and the ECC correction process. The CRC check acts as a mediator that identifies link errors with high confidence, enabling the system to distinguish between correctable storage errors and uncorrectable link errors, thus optimizing retry decisions.
2Productivity
If additional CRC check mechanism is implemented to differentiate error types, then retry operations are reduced and performance is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error detection and correction process into distinct stages: first CRC check for link error detection, then ECC correction for storage error handling. This segmentation allows each mechanism to specialize in specific error types, improving overall efficiency without requiring a completely new complex system.
Solution Approach 2:
The patent demonstrates multi-functionality by using the combined CRC-ECC mechanism to handle multiple types of errors (link errors and storage errors) with a unified error correction architecture. The same hardware infrastructure serves both error detection and correction purposes, reducing the need for additional dedicated components.
Data Source
AI summary
A system and a method are disclosed for error correction during operations of a memory system. For example, during a read operation, the error correction includes a read retry determination to account for link errors that are detectable by cyclic redundancy check (CRC) but not correctable by error correction coding (ECC). Reducing the number of read retry operations performed may improve system performance by reducing the number of clock cycles spent on retry operations that could have otherwise been allocated for other system services (e.g., completing read and write operations). Additional CRC calculations and checks may be used to determine when to perform a retry in addition to existing CRC and ECC checks, reducing the number of potential retry operations and improving system performance.