Post-Package Trim for 3D Memory Stacks
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Solution Overview
Problem
Integrated circuits, particularly memory devices, face failures due to manufacturing variability and mismatches in testing and field conditions, leading to reduced performance and reliability in systems like DRAM, as they are typically trimmed before packaging, which does not account for parasitic capacitance and unknown die positions in a stack.
Innovation Solution
The implementation of post-package trim (PPT) and soft post-package trim (SPPT) methods, which allow memory devices to be trimmed in a configuration closer to field conditions, using test mode control circuits, fuse logic, and serializers to adjust parameters like delay, voltage, and clock cycles, with the ability to store and override trim settings, and try various settings iteratively before committing to permanent changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory devices are trimmed before packaging, then manufacturing process can be simplified, but performance and reliability deteriorate due to manufacturing variability and mismatches in testing and field conditions
Solution Approach 1:
The patent applies preliminary action by performing initial trimming during manufacturing, then adding the capability to perform additional trimming after packaging. This allows the device to be prepared in advance with basic trim settings, while retaining the ability to make further adjustments later to account for field conditions and manufacturing variations, thus resolving the contradiction between manufacturing simplicity and field reliability.
Solution Approach 2:
The patent implements dynamics by transitioning from static pre-package trim settings to dynamic post-package trim capabilities. The memory device includes circuitry that allows trim parameters to be adjusted after packaging based on actual performance measurements and field conditions, making the trimming process adaptive rather than fixed, thereby improving reliability without complicating the initial manufacturing process.
2Reliability
If memory devices are trimmed in a stack configuration, then parasitic capacitance and unknown die positions can be accounted for, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies universality by designing a trimming system that can operate in multiple configurations - both individual die trimming and stack-based trimming. The same basic trim circuitry and control logic can handle different stacking arrangements and configurations, making the system versatile enough to account for parasitic capacitance and die positions without requiring entirely separate complex manufacturing processes for each configuration.
Data Source
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AI summary
Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (TSVs) can permit signals to pass vertically through the three-dimensional integrated circuit. Disclosed herein are apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory die is stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.