Post-Passivation Interconnect Bridge for IC Package Stress Distribution

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Solution Overview

Problem

The challenge in integrated circuit packaging lies in miniaturizing semiconductor devices while integrating large analog components like capacitors and inductors, and in achieving reliable interconnects with copper pads, as conventional gold wire bonding technologies face issues with pad oxidation and inefficient integration configurations.

Innovation Solution

The solution involves forming an integrated circuit package system with post-passivation interconnection and integration, including a first metal layer, a bridge, and bump pads connected to the bridge, which provides flexible connectivity and reduces stress on the pads, allowing for symmetrical stress distribution and improved integration of analog circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional gold wire bonding technology is used for copper pads, then interconnect reliability is maintained, but pad oxidation occurs which inhibits bonding process

Engineering Contradiction:
Improveinterconnect reliabilityVSAvoidpad oxidation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by forming a protective passivation layer over the copper pad before the bonding process. This pre-protection prevents oxidation from occurring during subsequent manufacturing steps, eliminating the need for gold plating while maintaining bonding reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary protective layer (passivation layer) between the copper pad and the oxidizing environment. This intermediary prevents direct contact between copper and oxygen, solving the oxidation problem without requiring gold plating.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If large analog components like capacitors and inductors are integrated into ICs, then mixed-signal design capability is improved, but device size increases

Engineering Contradiction:
Improvemixed-signal design capabilityVSAvoiddevice size
Core Design Contradiction:
Adaptability or versatilityVSVolume of moving object

Solution Approach 1:

The patent moves analog components from the traditional planar layout to a three-dimensional configuration using post-passivation interconnect layers. By stacking components vertically across multiple layers, the design achieves mixed-signal integration without proportionally increasing the device footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nesting by placing analog components and their interconnect structures within and across multiple passivation layers. This nested arrangement allows capacitors and inductors to be integrated within the IC structure without occupying excessive lateral space.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Adaptability or versatility

If post-passivation interconnection with bridges and bump pads is implemented, then flexible connectivity and stress distribution are improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveflexible connectivityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the interconnection structure into distinct functional elements: bridges for stress distribution, bump pads for connectivity, and multiple passivation layers for protection. This segmentation allows each element to be optimized independently while using standard semiconductor manufacturing processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar interconnection to three-dimensional post-passivation interconnection. By utilizing vertical stacking of metal layers and passivation layers, the design achieves flexible connectivity configurations without requiring complex lateral routing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Volume of moving object

If integrated circuit package dimensions are reduced, then space efficiency is improved, but integration of analog circuitry becomes more difficult

Engineering Contradiction:
Improvepackage dimensionsVSAvoidintegration of analog circuitry
Core Design Contradiction:
Volume of moving objectVSEase of manufacture

Solution Approach 1:

The patent resolves the space constraint by moving analog component integration into the vertical dimension through post-passivation layers. This allows capacitors and inductors to be formed above the substrate without increasing the lateral package footprint, maintaining ease of manufacturing while achieving compact dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8951904B2Integrated circuit package system with post-passivation interconnection and integration
Publication Date: 2015.02.10 JCET SEMICON (SHAOXING) CO LTD
  • US8951904B2 patent drawing
  • US8951904B2 patent drawing
  • US8951904B2 patent drawing

AI summary

An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.