Post-Passivation Interconnect Structure for Moisture Protection

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Solution Overview

Problem

The existing post-passivation interconnect structures in semiconductor devices face challenges in ball drop performance and reliability, particularly in preventing moisture attack and crack damage caused by the molding compound, which affects the thermal cycling life of the package assembly.

Innovation Solution

The formation of post-passivation interconnect (PPI) structures within a protective layer, followed by the creation of bumps and a molding compound layer, where the PPI structures are formed in the second protective layer to prevent moisture attack and reduce crack damage, and the method allows for a low-cost structure without additional masks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If post-passivation interconnect structures are formed on the surface, then ball drop performance improves, but the structure becomes more complex and costly

Engineering Contradiction:
Improveball drop performanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interconnect structure is divided into multiple segments: a first interconnect structure formed in the passivation layer, and a second interconnect structure formed in the protective layer. This segmentation allows each part to perform specific functions, improving ball drop performance while managing complexity through functional division.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first interconnect structure is embedded within the passivation layer, which itself is part of the protective layer structure. This nesting approach integrates multiple interconnect functions within a unified layered architecture, reducing overall structural complexity while maintaining reliability.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If additional protective layers are added to prevent moisture attack, then reliability improves, but manufacturing complexity increases

Engineering Contradiction:
Improvemoisture protectionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The protective layer serves multiple functions: it provides moisture protection, contains the second interconnect structure, and forms the bonding surface for bumps. This multi-functionality reduces the need for separate dedicated protective structures, simplifying manufacturing while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The passivation layer is formed first to provide initial moisture protection and electrical isolation, creating a stable foundation before forming the interconnect structures. This preliminary protective action simplifies subsequent manufacturing steps by establishing a ready-made protective barrier.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If PPI structures are formed within the molding compound, then crack damage is reduced, but process complexity increases

Engineering Contradiction:
Improvecrack damage resistanceVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protective layer acts as an intermediary between the molding compound and the interconnect structures. It provides a dedicated environment for forming the second interconnect structure with precise control over material properties and geometry, reducing crack damage while simplifying the overall process by separating the interconnect formation from the molding compound injection.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10777431B2Post-passivation interconnect structure and method of forming the same
Publication Date: 2020.09.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10777431B2 patent drawing
  • US10777431B2 patent drawing
  • US10777431B2 patent drawing

AI summary

A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.