Post-Passivation Interconnect Profile for Insulating Layer Conformity
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Solution Overview
Problem
In semiconductor manufacturing, the shrinking geometries of interconnect structures make it challenging to achieve adequate step coverage and conformity of insulating layers, leading to increased risks of cracking and collapsing during subsequent processes, which affects production yield and device reliability.
Innovation Solution
The use of PPI structures with specific profiles, such as barrel or trapezoidal shapes, formed through controlled etching processes, improves step coverage and conformity of insulating layers, reducing the risk of cracking and enhancing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If interconnect structures are shrunk to smaller geometries, then device density and integration are improved, but step coverage and conformity of insulating layers deteriorate
Solution Approach 1:
The patent applies parameter changes by modifying the etching process parameters (such as etch chemistry, power, pressure, and temperature) to achieve a controlled etch profile that improves step coverage. By adjusting these parameters, the etch process creates a more conformal insulating layer deposition on the shrunk interconnect structures, resolving the contradiction between smaller geometry and manufacturing precision.
2Device complexity
If insulating layers are deposited on shrunk interconnect structures, then device integration is improved, but cracking risk increases
Solution Approach 1:
The patent applies preliminary action by performing a specific etching process step before insulating layer deposition to pre-condition the interconnect structure surfaces. This preliminary etching creates optimal surface geometry and chemistry that enables subsequent insulating layers to deposit uniformly without forming cracks, thus preventing reliability issues before they occur.
Solution Approach 2:
The patent changes process parameters including etch selectivity, deposition temperature, and layer thickness ratios to ensure that insulating layers are deposited under conditions that minimize stress and prevent cracking, even on the complex geometries of shrunk interconnect structures.
3Ease of manufacture
If conventional etching processes are used, then manufacturing simplicity is maintained, but production yield decreases
Solution Approach 1:
The patent optimizes etching process parameters (gas flow rates, pressure, power, chemistry composition) to achieve a balance between process simplicity and high production yield. The optimized parameters create self-aligned features and improved step coverage that reduce defects and rework, thereby increasing yield without significantly complicating the manufacturing process.
Data Source
AI summary
An integrated circuit (IC) device includes a redistribution line over a substrate, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range. The IC device further includes a passivation layer over the redistribution line, wherein a bottommost surface of the passivation layer is below the bottommost surface of the redistribution line.