Post-Program Erase for 3D NAND Threshold Voltage Budget
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Solution Overview
Problem
Current memory technologies face challenges in efficiently programming and erasing memory cells in 3D NAND structures, particularly in maintaining a sufficient gap between erase and programmed states, which affects the threshold voltage budget and requires time-consuming and power-intensive verify processes.
Innovation Solution
The implementation of a post-program erase method that selectively erases only memory cells intended to remain in the erased state, inhibiting others from erase, and uses a single shorter erase pulse without verify, thereby increasing the threshold voltage budget and reducing power and time consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional erase-then-program approach is used, then memory cells are prepared for programming, but the threshold voltage budget is reduced and verify processes become time-consuming and power-intensive
Solution Approach 1:
The patent applies preliminary action by performing a post-program erase after the programming operation is complete. This reverse sequence allows the memory cells to be programmed first, establishing the threshold voltage, and then selectively erased to create the necessary gap without requiring a separate verify step, thereby resolving the time and power consumption issues while maintaining reliability
Solution Approach 2:
The patent inverts the traditional erase-then-program sequence by implementing program-then-erase. This inversion allows the programming operation to establish the threshold voltage first, and then the post-program erase creates the gap between erased and programmed states without requiring verification, effectively solving the contradiction between reliability and time loss
2Reliability
If a post-program erase is implemented, then the gap between erase and programmed states is enhanced, but additional erase operations are required
Solution Approach 1:
The patent applies local quality by selectively erasing only the memory cells that need to be in the erased state after programming, while leaving programmed cells unaffected. This selective post-program erase enhances the gap between states for the specific cells requiring it, without unnecessarily re-processing all cells, thus maintaining productivity while improving reliability
Solution Approach 2:
The patent uses partial action by applying erase conditions only to the subset of memory cells that need to be in the erased state, rather than erasing the entire array. This partial post-program erase sufficiently creates the necessary gap for reliability while avoiding excessive erase operations that would reduce productivity
3Reliability
If erase verify processes are performed, then data integrity is confirmed, but power consumption and processing time increase
Solution Approach 1:
The patent applies preliminary action by performing the erase operation after programming is complete, at which point the threshold voltage is already established. This timing allows the system to trust the programming result and eliminate the need for verify operations, thereby maintaining data integrity through the post-program erase while significantly reducing power consumption and processing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the gap between erase and programmed states, conserves power, and reduces processing time by eliminating the need for erase verify, while maintaining data integrity and efficiency in memory operations.
Implementation Method 1
Some memory cells may be programmed to a data state by storing charge in the memory cell. For example, the threshold voltage (Vt) of a NAND memory cell can be set to a target Vt by programming charge into a charge trapping layer.
Data Source
AI summary
Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.