Post-Routing Congestion Optimization With Cell Relocation
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Solution Overview
Problem
Existing semiconductor integrated circuit (IC) design processes face challenges in efficiently addressing hard-to-fix (HTF) DRC violations, particularly those occurring in clusters, which are difficult to resolve using conventional engineering change orders (ECOs) and manual fixes, leading to prolonged iteration times and increased complexity in reducing chip size.
Innovation Solution
A system and method employing cell relocation and anchor buffering techniques, facilitated by AI/ML-based classification, to optimize post-routing congestion and reduce DRC violations, including the use of a post-routing congestion optimization platform with engines for cell relocation, anchor buffering, and wire movement to address HTF DRC violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ECO and manual fixes are used to address HTF DRC violations, then the design can be modified, but the iteration time increases and complexity increases
Solution Approach 1:
The patent performs preliminary classification of DRC violations into HTF and non-HTF categories before attempting fixes. By identifying HTF violations early and applying specialized techniques (cell relocation, anchor buffering) specifically to these cases, the system avoids wasting time on conventional methods that would fail anyway, thereby reducing overall iteration time while maintaining high precision in resolution
Solution Approach 2:
The patent changes the approach parameter from conventional ECO/manual fixing to AI/ML-based classification and specialized techniques for HTF violations. This parameter change in the fixing methodology enables differentiated handling of violation types, improving resolution efficiency without sacrificing precision
2Manufacturing precision
If conventional ECO and manual fixes are used to address HTF DRC violations, then the design can be modified, but the process complexity increases
Solution Approach 1:
The patent segments the DRC violation fixing process into distinct categories: HTF violations and non-HTF violations. Each segment receives a tailored fixing approach (specialized techniques for HTF, conventional methods for others). This segmentation reduces overall process complexity by organizing the chaotic task of fixing all violations into manageable, differentiated streams with clear protocols
Solution Approach 2:
The patent introduces an AI/ML-based classification system as an intermediary between DRC violation detection and the fixing process. This intermediary automatically categorizes violations and routes them to appropriate fixing methods, reducing the complexity of manual judgment and process management while maintaining high resolution precision
3Productivity
If functional density is increased while geometry size decreases, then IC performance improves, but routing congestion increases making HTF DRC violations harder to fix
Solution Approach 1:
The patent applies local quality by treating different spatial regions of the IC layout differently. Instead of uniform fixing approaches, it identifies specific congested regions with HTF violations and applies specialized techniques (cell relocation to less congested areas, anchor buffering at critical points) localized to those problem areas. This allows high functional density to be maintained overall while locally resolving congestion-induced DRC violations
4Area of stationary object
If chip area is reduced to lower costs and shorten turn-around-time, then manufacturing efficiency improves, but routing congestion increases leading to more HTF DRC violations
Solution Approach 1:
The patent applies dimensionality change by using cell relocation to move cells from congested two-dimensional regions to less congested areas, effectively utilizing the layout space in a more distributed manner. Additionally, anchor buffering introduces a new dimensional approach by placing buffers at strategic points to extend routing paths around congestion zones, thereby maintaining manufacturing precision (low DRC violation rate) even when chip area is reduced
Data Source
AI summary
A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.