Post-Silicon Critical Point Identification Using Scan-Chain Flip-Flops
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Solution Overview
Problem
Existing methods fail to accurately identify critical points in integrated circuits (ICs) sensitive to operating voltage in the post-silicon stage, limiting the reduction of minimum operating voltage and leading to potential IC failures.
Innovation Solution
A test method and device that input test patterns into sample chips with sensor positions to generate mismatch counts and parameters, selecting specific chips and results to analyze and identify critical points, thereby enhancing circuit design and reducing minimum operating voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing margin sensors are incorporated into pre-silicon critical paths for post-silicon validation, then validation capability is improved, but area cost increases and coverage is reduced
Solution Approach 1:
The patent extracts the sensing function from dedicated sensor hardware and implements it using existing flip-flop elements in the scan-chain architecture. By repurposing existing circuit elements to serve dual functions (storage and sensing), the solution eliminates the need for separate sensor circuits, thereby reducing area cost while maintaining validation capability.
Solution Approach 2:
The patent makes the scan-chain flip-flops multi-functional by using them both for their original purpose (test pattern storage and result registration) and for sensing critical point violations. This universal usage of existing elements eliminates the need for dedicated sensors, resolving the area cost contradiction.
2Measurement precision
If more sensors are inserted for higher coverage, then validation accuracy is improved, but area cost increases
Solution Approach 1:
The existing scan-chain elements serve themselves dual purposes by automatically detecting critical point violations during normal test operations. The flip-flops that already exist in the circuit perform both their original test function and the additional sensing function, eliminating the need for external sensor components and enabling high coverage without area penalty.
3Reliability
If sensors are placed to detect all critical points, then detection coverage is improved, but device complexity increases
Solution Approach 1:
By making the scan-chain elements universal, the patent achieves comprehensive detection coverage without adding complex sensor placement infrastructure. The existing elements automatically cover all critical points along the scan-chain paths, simplifying the overall device architecture while maintaining high detection coverage.
Data Source
AI summary
A test method is provided for testing a circuit design. The test method includes inputting T test patterns into M sample chips to generate M test results where each sample chip is implemented with the circuit design and has N sensor positions, obtaining M mismatch counts of each sensor position according to the M test results, obtaining a mismatch parameter of the each sensor position according to the M mismatch counts of the each sensor position, selecting m sample chips from the M sample chips according to the M mismatch counts and the mismatch parameter of the each sensor position, selecting m test results from the M test results according to the m sample chips, and analyzing the m test results to obtain at least one critical point of the circuit design. M>m, and T, M, N and m are positive integers.