Post-Treated Masking Layer for Precise Nano-FET Patterning
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, challenges arise in efficiently forming and patterning semiconductor layers while maintaining the integrity and efficiency of transistor structures.
Innovation Solution
A method for forming nano-FETs involving the use of alternating semiconductor layers with high-etch selectivity, where regions dedicated to p-type and n-type transistors are masked and treated separately, followed by the formation of gate structures and interconnects on both sides of the transistor structures, enhancing the efficiency of the manufacturing process and ease of mask removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent applies segmentation by dividing the mask layer into multiple discrete layers (first mask layer and second mask layer) with different materials and functions. This allows independent processing and removal of each layer, simplifying the overall manufacturing process despite reduced feature sizes. The first mask layer is used for initial patterning while the second mask layer is used for subsequent processing steps, enabling complex nanoscale fabrication to be broken down into manageable sequential steps.
2Manufacturing precision
If mask layers are used for patterning semiconductor layers, then precise patterning is achieved, but mask layer removal becomes difficult
Solution Approach 1:
The patent applies parameter changes by selecting mask layer materials with distinctly different etch selectivities. The first mask layer is made of a material that can be selectively removed by a first etchant, while the second mask layer is made of a different material removable by a second etchant. This parameter differentiation (material composition) enables precise patterning during fabrication while facilitating easy and selective removal of each mask layer without affecting underlying structures or other mask layers.
3Productivity
If alternating semiconductor layers with high-etch selectivity are used, then patterning efficiency is improved, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming alternating semiconductor layers with high-etch selectivity before the patterning process. These layers are deposited in advance with controlled thicknesses and material compositions that provide the necessary etch selectivity differences. This preliminary preparation enables subsequent patterning steps to proceed efficiently with simple etching processes, as the selective etching behavior is already built into the layer structure rather than requiring complex real-time process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the efficiency of semiconductor device manufacturing by allowing precise patterning and easier removal of mask layers, thereby enhancing the integration density and performance of nano-FETs.
Implementation Method 1
performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer
Implementation Method 2
the performing of the first thermal treatment includes a radiation treatment
Data Source
AI summary
A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.