Postcoder Integration in SOVA Detector for High-Speed Decoding

Solution Overview

Problem

Existing communication systems face challenges in efficiently decoding data with high data rates while maintaining hardware area and power consumption within specified limits, particularly in high-speed applications like hard disk drives, due to the need for significant modifications in Soft Output Viterbi Algorithm (SOVA) trellis and trace back circuitry.

Innovation Solution

An area and power-efficient, high-speed implementation of a programmable postcoder is embedded in the SOVA design, allowing for conversion of channel domain information to user domain information without redesigning the trellis or trace back circuitry, utilizing a three-stage SOVA detector/decoder architecture with a postcoder that operates on a trellis of length GP and a reliability unit for soft information computation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If SOVA trellis and trace back circuitry are redesigned to support high data rates, then decoding performance is improved, but hardware area and power consumption increase

Engineering Contradiction:

Improvedata rateVSAvoidhardware area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The detector is divided into three distinct stages: a first stage for ML path estimation, a second stage with a postcoder for domain conversion, and a third stage for soft information computation. This segmentation allows each stage to be optimized independently, enabling high data rate operation without requiring complete redesign of the entire SOVA trellis and trace back circuitry, thus reducing overall hardware area requirements.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A postcoder is introduced as an intermediary component between the ML path estimation stage and the soft information computation stage. The postcoder converts channel domain information to user domain information, enabling the system to operate at high data rates without redesigning the core SOVA trellis structure, thereby reducing hardware area while maintaining decoding performance.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If SOVA trellis and trace back circuitry are redesigned to support high data rates, then decoding performance is improved, but power consumption increases

Engineering Contradiction:

Improvedata rateVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The detector is divided into three distinct stages: a first stage for ML path estimation, a second stage with a postcoder for domain conversion, and a third stage for soft information computation. This segmentation allows each stage to be optimized independently, enabling high data rate operation without requiring complete redesign of the entire SOVA trellis and trace back circuitry, thus reducing overall power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A postcoder is introduced as an intermediary component between the ML path estimation stage and the soft information computation stage. The postcoder converts channel domain information to user domain information, enabling the system to operate at high data rates without redesigning the core SOVA trellis structure, thereby reducing power consumption while maintaining decoding performance.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If SOVA trellis and trace back circuitry are redesigned to support high data rates, then decoding performance is improved, but device complexity increases

Engineering Contradiction:

Improvedata rateVSAvoidcircuitry complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The detector is divided into three distinct stages: a first stage for ML path estimation, a second stage with a postcoder for domain conversion, and a third stage for soft information computation. This segmentation allows each stage to be optimized independently, enabling high data rate operation without requiring complete redesign of the entire SOVA trellis and trace back circuitry, thus reducing overall device complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A postcoder is introduced as an intermediary component between the ML path estimation stage and the soft information computation stage. The postcoder converts channel domain information to user domain information, enabling the system to operate at high data rates without redesigning the core SOVA trellis structure, thereby reducing device complexity while maintaining decoding performance.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8885779B2Channel detector implementation with postcoder

Publication Date: 2014.11.11 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A signal detector/decoder is implemented in multiple stages. The beginning stage is configured to input channel data bits and to output hard data bits based on the channel bits and a maximum likelihood (ML) path. The next stage includes a postcoder coupled to receive channel domain information from the first stage and to convert the channel domain information to user domain information. The final stage includes a reliability unit coupled to receive the user domain information from the postcoder and to output user domain soft information for the hard data bits based on the ML path estimation and the user domain information.