Selective Posted Data Error Detection for Memory Subsystems
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Solution Overview
Problem
The increasing number of processor cores in chip design leads to higher bit error rates, which necessitates more robust error-correcting codes, increasing memory access latency, while DRAM access latency has not kept pace with processor core clock rates, limiting the effectiveness of on-chip cache improvements.
Innovation Solution
The solution involves selective application of posted error detection processing, where data is transmitted to the requestor before or after error detection completion based on access type or error history, and speculative execution of instructions dependent on high latency operations, allowing for reduced memory access latency and improved resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If robust error-correcting codes (ECC and CRC) are implemented to handle higher bit error rates from increased processor core counts, then data integrity is improved, but memory access latency increases due to deeper error correction logic pipelines
Solution Approach 1:
The system performs error detection processing in advance during data retrieval from memory, before the data is actually needed by the processor cores. By pre-detecting errors and preparing corrected data or error flags ahead of time, the system eliminates the need for deep error correction pipelines during critical data access operations, thus reducing memory access latency while maintaining data integrity
Solution Approach 2:
The error detection and correction process is divided into separate stages: error detection is performed during data retrieval, while error correction is handled separately and asynchronously. This segmentation allows the critical data path to proceed without waiting for complete error correction, reducing latency while still ensuring data integrity through subsequent correction of detected errors
2Loss of time
If on-chip cache hierarchies are enlarged to buffer frequently used data closer to processor cores, then effective memory access latency is improved, but chip size increases, forcing a tradeoff between the number of processor cores and cache memory capacity
Solution Approach 1:
The system changes the operational parameters of the cache hierarchy by implementing selective caching strategies and optimizing cache replacement policies based on access patterns. By dynamically adjusting cache behavior rather than simply increasing cache capacity, the system achieves improved effective memory access latency without requiring additional chip area for cache memory
Data Source
AI summary
In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.