Selective Posted Data Error Detection for Memory Access Latency
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Solution Overview
Problem
The increasing number of processor cores in chip design leads to higher bit error rates, which necessitates more robust error-correcting codes, increasing memory access latency, while DRAM access latency has not kept pace with processor core clock rates, limiting the effectiveness of on-chip cache improvements.
Innovation Solution
The solution involves selective application of posted error detection processing, where data is transmitted before or after error detection completion based on access type or error history, and speculative execution of instructions dependent on high latency operations, allowing for reduced memory access latency and improved resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If robust error-correcting codes (ECC and CRC) are implemented to ensure data integrity, then reliability is improved, but memory access latency increases due to deeper error correction logic pipelines
Solution Approach 1:
The patent applies preliminary action by performing error detection processing in advance before data is needed, and by speculatively executing instructions that depend on high-latency memory operations. The system predicts which instructions can be executed without waiting for memory completion, thereby reducing the effective latency impact of robust error correction codes.
Solution Approach 2:
The patent implements dynamics by making the error detection processing timing adaptable rather than fixed. The system dynamically selects between completing error detection before data transmission or allowing data transmission to proceed with posted error detection, based on the specific memory access characteristics and instructions being executed.
2Loss of time
If on-chip cache capacity is increased to buffer frequently used data closer to processor cores, then effective memory access latency is improved, but chip size increases which limits the number of processor cores that can be included
Solution Approach 1:
The patent uses preliminary action through speculative execution of instructions. Instead of increasing cache capacity to predict what data will be needed, the system predicts which instructions can execute without waiting for data, thereby reducing latency without requiring more cache memory or chip area.
Solution Approach 2:
The patent changes the parameter of instruction execution timing from sequential to speculative. By allowing instructions to be executed before data is actually available from memory, the system effectively reduces the impact of memory latency without changing the physical cache architecture or chip size.
3Productivity
If the number of processor cores per chip is increased to improve productivity, then computing capability is improved, but bit error rates on interconnects and external memory increase
Solution Approach 1:
The patent applies preliminary action by performing error detection in advance and by speculatively executing instructions that do not depend on potentially erroneous data. This allows the system to maintain high productivity with multiple cores while proactively managing the increased bit error rates through predictive error detection and instruction scheduling.
Solution Approach 2:
The patent implements feedback mechanisms through posted error detection processing. The system continuously monitors for errors in memory data and provides feedback to adjust instruction execution accordingly. This feedback loop allows the system to maintain reliability despite the higher bit error rates introduced by increased processor core density.
Data Source
AI summary
In a data processing system, a selection is made, based at least on an access type of a memory access request, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.