Posted Interrupt Vector Atomic Bit Setting for PCIe Virtualization
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Solution Overview
Problem
Existing interrupt virtualization hardware does not effectively deliver device-sourced interrupts directly to a running virtual central processing unit (VCPU), requiring either a dedicated hypervisor core or tolerating intercepts on VCPUs, which is inefficient.
Innovation Solution
A PCIe device uses limited interrupt virtualization hardware to atomically set bits in a posted interrupt vector (PIV) of a target CPU, sending a notification interrupt to the CPU, employing methods such as compare-and-swap, fetch-and-add instructions, PCIe byte enables, and helper CPU assistance to ensure atomicity and proper interrupt delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If standard MSI or MSI-X interrupts are used with existing interrupt virtualization hardware, then interrupt delivery can be achieved, but the interrupt must trip through the hypervisor causing increased latency and requiring dedicated hypervisor cores or tolerating intercepts
Solution Approach 1:
The patent introduces an intermediary mechanism (the posted interrupt vector register and notification mechanism) that enables direct interrupt delivery from the PCIe device to the VCPU without requiring the interrupt to trip through the hypervisor. This intermediary structure allows the VCPU to be notified directly of interrupt events, eliminating the latency and complexity associated with hypervisor-mediated interrupt handling.
2Reliability
If a dedicated hypervisor core is used for handling interrupts, then interrupt handling is reliable, but system resource utilization decreases due to dedicating a core
Solution Approach 1:
The patent implements a self-service mechanism where the VCPU can directly receive and handle interrupts without requiring a dedicated hypervisor core. The posted interrupt vector register and notification mechanism enable the VCPU to autonomously detect and respond to interrupt events, eliminating the need for dedicated hypervisor resources while maintaining reliable interrupt handling.
3Measurement precision
If atomic bit setting is implemented in the posted interrupt vector, then interrupt delivery accuracy is improved, but hardware complexity increases due to required atomic operations
Solution Approach 1:
The patent uses the posted interrupt vector register as an intermediary structure that inherently supports atomic bit setting operations. This register serves as a notification mechanism where individual bits can be atomically set to indicate specific interrupt conditions, providing precise interrupt delivery while managing hardware complexity through a dedicated notification structure.
Data Source
AI summary
A system and method are provided for generating interrupts in a computer system using limited interrupt virtualization hardware. A peripheral component interconnect express (PCIe) device atomically sets one or more bits in a posted interrupt vector (PIV) of a target central processing unit (CPU), and sends an interrupt to the target CPU, the interrupt notifying the target CPU of changes to the PIV. Atomically setting the one or more bits may include executing a compare-and-swap function, executing a fetch-and-add instruction to increment a DWORD corresponding to the one or more bits in the PIV by a value of 2 ^ (b mod 32), using PCIe byte enables to write to a single byte in the PCIe address space that contains the one or more bits, using a helper CPU, performing a PCIe swap to the PIV, or storing the PIV in a memory of the PCIe device.