PoSt FET Memory Non-Destructive Read via Strain Coupling

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Solution Overview

Problem

Ferroelectric-based non-volatile memory cells face issues with destructive reads and low fidelity during read operations, which affect the reliability of maintaining digital bit values.

Innovation Solution

A polarization-induced strain coupled two-dimensional field effect transistor (PoSt FET) memory cell utilizing a piezoelectric/ferroelectric layer between the gate and back contact, with a specific ratio of cross-sectional areas, enables non-destructive read operations by transferring polarization-induced strain to the channel for dynamic bandgap modulation and bit sensing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If ferroelectric-based memory is used for non-volatile storage, then low power write operations are achieved, but destructive read operations occur

Engineering Contradiction:
Improvepower consumption during writeVSAvoidread operation non-destructiveness
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

A piezoelectric layer is introduced as an intermediary between the ferroelectric layer and the channel. This piezoelectric layer converts electrical polarization signals into mechanical strain, which then modulates the channel conductivity. This intermediary mechanism enables non-destructive read operations by sensing strain rather than directly measuring electrical properties that would collapse the ferroelectric state.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces traditional electrical read mechanisms with a mechanical strain-based sensing mechanism. The piezoelectric layer transduces ferroelectric polarization into mechanical strain, and this strain is detected through changes in channel conductivity. This mechanical substitution allows reading without directly perturbing the ferroelectric polarization state, eliminating destructive reads.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of operation

If conventional read mechanisms are used in ferroelectric memory, then read operations are simple, but fidelity of bit value detection is low

Engineering Contradiction:
Improveread operation simplicityVSAvoidbit value detection fidelity
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent replaces conventional electrical read mechanisms with a mechanical strain-based sensing approach. The piezoelectric layer converts ferroelectric polarization states into distinct mechanical strain states, which produce measurable changes in channel conductivity. This mechanical substitution enhances detection fidelity by creating larger, more distinguishable signal differences between logic states while maintaining operational simplicity through standard FET readout circuits.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the physical parameter used for read detection from direct electrical measurement to mechanical strain measurement. By utilizing the piezoelectric effect, the system transforms the ferroelectric polarization parameter into a mechanical strain parameter that can be sensed with higher fidelity through channel conductivity changes, improving bit value detection accuracy.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If piezoelectric/ferroelectric layer area is increased to improve strain transfer, then channel area must increase, but device area increases

Engineering Contradiction:
Improvestrain transfer efficiencyVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by concentrating the piezoelectric/ferroelectric layer directly beneath the channel region where strain transfer is most critical. This localized placement ensures that strain is applied precisely where needed to modulate channel conductivity, maximizing strain transfer efficiency without requiring a large overall device area. The piezoelectric layer area is optimized to match the channel area, creating a focused interaction zone.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs asymmetric area ratios between the piezoelectric layer and the channel, with the piezoelectric layer having a larger cross-sectional area than the channel (area ratio of 0.03 to 0.07). This asymmetric design ensures complete coverage of the channel by the piezoelectric layer, maximizing strain transfer efficiency while controlling overall device area through the controlled area ratio.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The PoSt FET memory cell achieves high fidelity and low power non-destructive read operations while maintaining the low power electric-field driven write attributes of ferroelectric-based memories, enhancing the reliability of bit value retention.

Implementation Method 1

A polarization induced strain coupled two dimensional field effect transistor (PoSt FET) memory cell utilizes a piezoelectric/ferroelectric layer between the gate and back contact, with a specific ratio of cross-sectional areas, enables non-destructive read operations by transferring polarization-induced strain to the channel for dynamic bandgap modulation

Methodology Applied
Scientific EffectPiezoelectric effect: Piezoelectric Effect

Data Source

PatentUS11296224B1Non-volatile polarization induced strain coupled 2D FET memory
Publication Date: 2022.04.05 PURDUE RES FOUND
  • US11296224B1 patent drawing
  • US11296224B1 patent drawing
  • US11296224B1 patent drawing

AI summary

A polarization induced strain coupled two dimensional field effect transistor (PoSt FET) memory cell is disclosed which includes a transistor including a source contact, a drain contact, a gate contact, a back contact, a channel disposed atop the gate contact, wherein the channel and the gate are separated by an electrically insulating material, and a piezoelectric (PE)/ferroelectric(FE) (PE/FE) layer disposed between the gate contact and the back contact and configured to store bit information in form of ferroelectric polarization (P), wherein a ratio of cross-sectional area of the channel to cross-sectional area of the PE/FE layer is between about 0.03 to about 0.07.