Contributor-Based Power Abstract for Clock Gating Domains
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Solution Overview
Problem
Aggressively clock gated designs in modern electronic devices pose challenges in accurately analyzing power consumption due to their complexity, making traditional PVT-specific power models nearly impossible to use, especially in full chip power analysis.
Innovation Solution
The method involves generating a contributor-based power abstract by identifying clock power components, switching characteristics, and effective capacitance for each clock gating domain, combining these into a domain combination list, performing per-case simulations, and calculating effective capacitance to create a PVT-independent power abstract.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PVT-specific power models are used for full chip power analysis, then the analysis can be performed with conventional methods, but the accuracy of power analysis for aggressively clock gated designs deteriorates and becomes nearly impossible
Solution Approach 1:
The patent segments the complex clock gated design into multiple clock gating domains, each with its own power abstraction model. By dividing the full chip into manageable domains and creating separate power models for each, the system can handle the complexity of aggressive clock gating while maintaining accurate power analysis through compositional aggregation of domain-level results.
2Use of energy by moving object
If aggressive clock gating is implemented to reduce power consumption, then energy efficiency improves, but the complexity of power modeling increases and traditional methods become inadequate
Solution Approach 1:
The patent changes the parameters used in power modeling by introducing domain-specific parameters such as switching activity factors, clock gating ratios, and effective capacitance values. These parameter transformations enable accurate power analysis for aggressively clock gated designs by capturing the nonlinear and variable power consumption characteristics that traditional PVT-specific models cannot represent.
3Measurement precision
If detailed per-domain power analysis is performed for each clock gating domain, then measurement precision improves, but computational time and resources increase
Solution Approach 1:
The patent performs preliminary actions by pre-characterizing each clock gating domain and generating power abstraction models during the design phase, before full chip simulation. This preliminary power modeling captures domain-specific characteristics including switching activity and clock gating behavior, enabling fast and accurate power estimation during later analysis stages without requiring exhaustive computational resources.
Data Source
AI summary
Generating a contributor-based power abstract for a device, including: identifying a clock power component for each of a plurality of clock gating domains, identifying a switching characteristic for each of the clock gating domains, combining the switching characteristics for all of the clock gating domains into a domain combination list, performing a per-case simulation based at least on the domain combination list, calculating an effective capacitance for each of the clock gating domains based at least on the per-case simulation, and generating a power abstract for each of the clock gating domains based at least on the effective capacitance.