Power Amplifier FET Biasing for gm3 and IM3 Linearization
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Solution Overview
Problem
Existing power amplifiers face challenges in achieving linear gain and minimizing third-order transconductance (gm3) values, which lead to nonlinear distortion in amplified signals.
Innovation Solution
The power amplifier design incorporates multiple field-effect transistors (FETs) biased by the same gate voltage bias, with modulated gate widths and pinch-off voltages to minimize gm3 values, while applying derivative superposition techniques to optimize performance parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple FETs with different gate widths and pinch-off voltages are used, then linearity and gm3 minimization are improved, but device complexity increases
Solution Approach 1:
The power amplifier is divided into multiple parallel FET branches, each with different gate widths and pinch-off voltages. This segmentation allows each FET to contribute differently to the overall transconductance, enabling precise control of gm3 and improvement of linearity through the superposition of their individual characteristics.
Solution Approach 2:
Each FET in the parallel configuration is designed with specific local characteristics (different gate widths and pinch-off voltages) optimized for particular operating conditions. This local quality differentiation allows the amplifier to maintain optimal performance across a wider range of gate voltages while minimizing third-order transconductance at each operating point.
2Object-generated harmful factors
If auxiliary biasing devices are added to minimize gm3, then third-order intermodulation is reduced, but device complexity increases
Solution Approach 1:
The invention converts the potentially harmful third-order transconductance components generated by individual FETs into beneficial effects by carefully selecting their characteristics. The auxiliary biasing devices generate third-order components that, when superimposed with the main amplifying device, result in cancellation or minimization of the overall third-order intermodulation distortion.
Solution Approach 2:
The auxiliary biasing devices are pre-configured with specific gate widths and pinch-off voltages to generate third-order transconductance components that counteract the harmful effects before they manifest as intermodulation distortion. This preliminary anti-action is achieved through careful design of the FET parameters to create opposing third-order effects.
Data Source
AI summary
Examples of the disclosure include a power amplifier comprising an input to receive an input signal, an output to provide an amplified output signal, a gate voltage bias node to receive a gate voltage bias signal, a first amplifier device having a first gate connection coupled to the gate voltage bias node and configured to receive the gate voltage bias signal, and a second amplifier device having a second gate connection coupled to the gate voltage bias node and configured to receive the gate voltage bias signal.