Switching Power Amplifier Harmonic Suppression by Duty-Cycle Superposition
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Solution Overview
Problem
Conventional switching power amplifiers with high-order matching networks and on-chip harmonic traps fail to effectively suppress electromagnetic emissions at harmonics, leading to inefficiencies and increased component complexity, while existing harmonic suppression methods reduce output power at the fundamental frequency.
Innovation Solution
A switching power amplifier with a polyphase converter and power amplifier stage that generates 50% and 25% duty cycle rail-to-rail signals to superimpose output currents, achieving harmonic cancellation and meeting spectral mask requirements without additional external passives or on-chip inductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If high-order matching networks are used to reduce conducted harmonic power, then harmonic emissions are reduced, but the number of components increases and EM radiation from bondwires and PCB loops is not effectively addressed
Solution Approach 1:
The patent extracts the harmonic suppression function from external components (matching networks, off-chip filters) and implements it directly within the power amplifier circuitry through duty-cycle modulation and current cancellation techniques, eliminating the need for additional external passive components
Solution Approach 2:
The power amplifier output stage performs multiple functions simultaneously: it amplifies the fundamental frequency signal while also generating controlled harmonic cancellation currents through duty-cycle modulation, eliminating the need for separate harmonic filtering components
2Object-generated harmful factors
If on-chip passive devices are used for harmonic traps, then radiated harmonic power is reduced, but valuable circuit area is consumed and Q factor limitations bound the maximum achievable suppression
Solution Approach 1:
The patent eliminates the need for on-chip passive harmonic trap devices by implementing harmonic suppression through active duty-cycle modulation and current cancellation in the power amplifier stage, freeing up valuable chip area
Solution Approach 2:
The patent replaces passive LC resonator-based harmonic traps with an active electronic control mechanism using duty-cycle modulation and transistor switching to achieve harmonic cancellation, avoiding Q factor limitations and area constraints of passive devices
3Object-generated harmful factors
If transient metrics are controlled to reduce harmonic content, then harmonic emissions are reduced, but efficiency decreases significantly due to reduced output power at fundamental frequency
Solution Approach 1:
The patent segments the power amplifier output stage into multiple parallel branches with different duty cycles, allowing independent control of fundamental frequency power and harmonic cancellation currents, enabling simultaneous high efficiency and low harmonic emissions
Solution Approach 2:
The patent uses periodic duty-cycle modulation of the power amplifier switching transistors to generate fundamental frequency output power while simultaneously creating controlled harmonic cancellation currents, maintaining efficiency by not altering the overall switching frequency or duty cycle average
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses third and fifth harmonics, maintaining efficiency and reducing radiated spectral emissions, while minimizing the complexity of external matching networks and enhancing silicon validation time.
Implementation Method 1
The polyphase filter converts a sinusoidal input signal into a positive 45 degree phase-shifted sinusoidal signal, a non-shifted amplitude adjusted sinusoidal signal, and a negative 45 degree phase-shifted sinusoidal signal
Implementation Method 2
The transistors of the first branch have control terminals receiving the 50% duty cycle rail-to-rail signal. The P-channel transistor of the second branch has a control terminal receiving the negative 25% duty cycle rail-to-rail signal. The N-channel transistor of the second branch has a control terminal receiving the positive 25% duty cycle rail-to-rail signal
Implementation Method 3
The first branch generates a first output current having about a 50% duty cycle, and the second branch generates a second output current having about a 25% duty cycle that is superimposed together with the first output current. The collective superimposed current performs harmonic cancellations, including, for example, suppressing the third and fifth harmonics at the output
Data Source
AI summary
A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.