Integrated Power Amplifier Feedback for Stable Output Impedance

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Solution Overview

Problem

Conventional power amplifiers suffer from high bias current noise, non-linear transfer functions, and inaccurate output impedance, particularly over a narrow frequency band, leading to inefficient power delivery and interference with other frequency bands.

Innovation Solution

A power amplifier topology with a buffer stage and feedback system, where the current from a first transistor is copied and multiplied by a factor (n) in a second transistor, and fed back to the first transistor, allowing for a constant and defined output impedance over a large frequency range through the use of resistors RF and RG, and feedback loops for noise suppression.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If large bias current is used in the transistor to ensure compliance to output requirements, then output power delivery is improved, but noise increases

Engineering Contradiction:
Improveoutput power deliveryVSAvoidnoise
Core Design Contradiction:
PowerVSObject-generated harmful factors

Solution Approach 1:

The patent implements a feedback mechanism where the output current is sensed and fed back to the input stage through a feedback network. This allows the amplifier to maintain accurate output current control without requiring excessive bias current, thereby reducing noise while preserving power delivery capability. The feedback loop continuously adjusts the operating point to optimize both power output and noise performance.

Inventive Principle:
Principle #23Feedback

2Device complexity

If conventional power amplifier topology is used, then simplicity is maintained, but linearity deteriorates due to non-linear transfer function

Engineering Contradiction:
Improvetopology simplicityVSAvoidlinearity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent employs feedback to linearize the transfer function by sensing the actual output and comparing it with the desired output. The error signal is then used to correct deviations caused by transistor non-linearity. This approach maintains the basic amplifier topology while significantly improving linearity through the feedback control mechanism.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent utilizes dynamic parameter changes in the feedback network, specifically varying the effective feedback factor based on operating conditions. By adjusting feedback parameters adaptively, the system compensates for non-linearities across different output power levels, maintaining high linearity without requiring a completely different topology.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If output impedance is dependant on transistor behavior, then device simplicity is maintained, but output impedance accuracy deteriorates over wide frequency band

Engineering Contradiction:
Improveimpedance definition simplicityVSAvoidoutput impedance accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements impedance feedback where the output impedance is deliberately defined by feedback network components rather than transistor characteristics. The feedback loop senses output voltage and current, and the feedback network is designed to present a precise, frequency-stable impedance. This decouples output impedance from transistor variations and extends accuracy across a wide frequency band.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8018284B2Method of using integrated power amplifier
Publication Date: 2011.09.13 NXP BV
  • US8018284B2 patent drawing
  • US8018284B2 patent drawing
  • US8018284B2 patent drawing

AI summary

An output-impedance in a power amplifier is provided. A first transistor QBUF of a buffer stage is connected to a first side of a resistor RF and a second transistor QAMP to a second opposite side of the resistor RF. The first transistor feeds a current IRF to the second resistor QAMP. The current IRF at the second transistor is copied and multiplied by a factor (n) to form an output current IOUT, as (1+n)*IRF. The current IRF is fed back to the first transistor and the output current IOUT is fed to a load resistor R.