Power-Aware Debugging System for IC Design
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Solution Overview
Problem
Debugging power-aware integrated circuit designs is challenging due to the lack of consideration for Power Definition Markup Language (PDML) aspects in conventional debugging tools, leading to tedious and error-prone processes when determining the causes of unexpected signal values.
Innovation Solution
An automated power-aware debugging system that generates annotated displays of HDL code and signal traces, incorporating PDML models to relate power intent to HDL designs, and provides warnings for illegal power states, facilitating the identification of power-related issues in IC designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional debugging tools are used for power-aware IC designs, then the debugging process becomes tedious and error-prone, but the tools lack the capability to model power management behavior
Solution Approach 1:
The patent introduces an intermediary component that bridges the HDL design model and the PDML power model. This intermediary enables the debugging tool to access and interpret power management behavior described in PDML, allowing conventional debugging tools to work effectively with power-aware designs without requiring complete redesign of the debugging infrastructure
Solution Approach 2:
The debugging tool is enhanced to handle multiple types of data simultaneously - both traditional HDL design data and PDML power management data. This multi-functionality allows a single tool to perform both conventional debugging and power-aware debugging, eliminating the need for separate specialized tools
2Use of energy by moving object
If power management techniques such as power gating and multi-voltage domains are implemented, then power consumption is reduced, but the design process becomes more complex and prone to unanticipated bugs
Solution Approach 1:
The patent enables power management behavior to be specified and verified at the RTL or architecture stage using PDML, before the design is implemented in gate-level HDL code. This preliminary action allows designers to plan and validate power management strategies early in the design process, avoiding the introduction of bugs late in the design flow
Solution Approach 2:
The debugging tool provides feedback by comparing the simulated behavior of the HDL design against the power intent specified in PDML. When discrepancies are detected, such as unexpected signal values in power domains, the tool alerts designers to potential errors in power management implementation, allowing for corrective action before fabrication
3Loss of energy
If power gating is implemented with retention cells and isolation cells, then dynamic power consumption is reduced, but the debugging process becomes more difficult due to additional components
Solution Approach 1:
The debugging tool enhances visual display capabilities to provide distinctive visual indicators for power domain states. Different visual representations (such as color coding or symbolic annotations) are used to show whether power domains are active or gated, and to indicate the state of retention and isolation cells, making it easier for designers to interpret complex power-aware designs at a glance
Data Source
AI summary
A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.