Power-Aware Hash Function for Multi-Core Cache Slices
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Solution Overview
Problem
Multi-core processing chips face challenges in efficiently managing power consumption across multiple last-level caches, leading to increased energy expenditure and performance inefficiencies due to the need to maintain all caches active, even when some are idle.
Innovation Solution
Implementing a dual hashing function system where processor cores map access addresses to all active last-level caches using a first hashing function when all caches are active, and switch to a second hashing function that only accesses active caches when some caches are in a low power mode, thereby avoiding unnecessary 'write-through' to main memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all last-level caches are maintained in high power consumption mode to ensure data availability, then data access reliability is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the operational state of last-level caches based on actual access needs. The hash function is modified to map cache accesses only to currently active caches, allowing caches to transition between active and low-power states. This dynamic adaptation resolves the contradiction by maintaining data access reliability through selective cache activation while reducing overall power consumption by keeping caches in low-power mode when not needed.
2Use of energy by moving object
If some last-level caches are placed in low power consumption mode to reduce energy expenditure, then power consumption is reduced, but data access performance deteriorates due to write-through to main memory
Solution Approach 1:
The system changes the parameters of the hash function based on the operational state of caches. When caches are in low-power mode, the hash function parameters are adjusted to map accesses only to active caches, preventing write-through operations. This parameter adaptation resolves the contradiction by maintaining data access performance through intelligent access routing while enabling power savings through selective cache deactivation.
3Device complexity
If a fixed hashing function is used for cache mapping, then implementation simplicity is maintained, but system adaptability to dynamic power states is reduced
Solution Approach 1:
The hash function transitions from a static implementation to a dynamic one that adapts to cache power states. The system monitors the operational state of caches and selectively applies different hash function variants (first hash function for all caches active, second hash function for subset active). This dynamic approach resolves the contradiction by providing system adaptability to varying power states while maintaining implementation simplicity through the use of standardized hashing algorithms with configurable active cache sets.
Data Source
AI summary
A multi-core processing chip where the last-level cache functionality is implemented by multiple last-level caches (a.k.a. cache slices) that are physically and logically distributed. The hash function used by the processors on the chip is changed according to which of last-level caches are active (e.g., ‘on’) and which are in a lower power consumption mode (e.g., ‘off’.) Thus, a first hash function is used to distribute accesses (i.e., reads and writes of data blocks) to all of the last-level caches when, for example, all of the last-level caches are ‘on.’ A second hash function is used to distribute accesses to the appropriate subset of the last-level caches when, for example, some of the last-level caches are ‘off.’ The chip controls the power consumption by turning on and off cache slices based on power states, and consequently dynamically switches among at least two hash functions.