Power Aware Latch Weighting for Scan Chain Power Reduction
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Solution Overview
Problem
Conventional electronic testing methods experience high power consumption during operational speed testing, leading to test failures and stress-related issues due to increased switching power, which existing heuristic methods fail to adequately address by not considering actual circuit topology.
Innovation Solution
A system comprising a circuit analysis module, don't-care analysis module, and sub-circuit exception module that analyzes the device under test to identify sub-circuits and assign weighted input values to don't-care latches based on their logical description, reducing power consumption by selectively setting bit positions to minimize switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If testing is performed at operational speed, then test accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies different fill strategies to different portions of the DUT based on their testing requirements. Critical sub-circuits receive targeted test patterns while non-critical portions use don't-care bit optimization, allowing speed testing in critical areas without overwhelming power consumption across the entire device.
Solution Approach 2:
The patent divides the DUT into distinct sub-circuits and applies power management strategies selectively. By identifying and isolating specific sub-circuits for testing, the system can maintain operational speed for accuracy while limiting power consumption to only the necessary testing portions.
2Reliability
If don't-care bits are randomly filled, then fault coverage is slightly improved, but power consumption increases
Solution Approach 1:
The patent changes the parameter of don't-care bit fill values from random to strategically determined values based on circuit topology analysis. This parameter change reduces the number of transitions in don't-care bits while maintaining fortuitous detection capability, thereby reducing power consumption without significantly compromising fault coverage.
Solution Approach 2:
The system uses circuit topology information and transition analysis to feedback-determine optimal fill values for don't-care bits. This feedback mechanism allows the system to select fill values that minimize transitions and power consumption while preserving the ability to detect unexpected faults.
3Use of energy by moving object
If test frequency is lowered to reduce power, then power consumption decreases, but test time increases
Solution Approach 1:
The patent applies power reduction strategies selectively to don't-care bits rather than uniformly across all test signals. Critical test signals maintain high frequency for speed testing, while don't-care bits use optimized fill values to reduce transitions, achieving localized power reduction without compromising overall test time.
4Ease of manufacture
If conventional heuristic methods are used for don't-care filling, then implementation is simple, but circuit topology is not considered
Solution Approach 1:
The patent performs preliminary analysis of circuit topology and identifies critical sub-circuits before generating test patterns. This preliminary action enables the system to make informed decisions about don't-care bit fill values based on actual circuit structure, improving power efficiency without requiring complex real-time adjustments during testing.
Data Source
AI summary
A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.