Power-Aware RAM Processing via Automated Memory Mapping
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Solution Overview
Problem
Current programmable devices require manual optimization of logical and physical memories for reduced power consumption, which is time-consuming, error-prone, and challenging due to the need for extensive expertise and adherence to timing and area constraints.
Innovation Solution
An automated method that maps logical memories and logic functions to power-optimized physical implementations, using techniques such as clock enable signals to deactivate unused memory access ports and slicing logical memories into embedded memory blocks to minimize power consumption, while ensuring compliance with design constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If manual optimization of logical and physical memories is performed, then power consumption can be reduced, but the process becomes time-consuming and error-prone
Solution Approach 1:
The system performs automatic power optimization of memory mappings without requiring manual designer intervention. The compilation tool autonomously evaluates multiple memory mapping options, estimates their power consumption using activity trace analysis, and selects the optimal configuration, thereby eliminating the time-consuming and error-prone manual optimization process while achieving power reduction
Solution Approach 2:
The system uses activity trace information from simulated or actual device operation to feedback into the power estimation model. This feedback loop allows the automatic optimization process to accurately predict power consumption of different memory mappings and iteratively improve the selection, resolving the contradiction between automation and optimization effectiveness
2Loss of energy
If manual optimization is performed to reduce power consumption, then energy efficiency improves, but the process becomes complex and error-prone due to timing and area constraints
Solution Approach 1:
The compilation tool automatically handles the complex power optimization process by integrating power estimation, constraint checking, and mapping selection into a unified automated workflow. This eliminates the need for designers to manually navigate complex optimization trade-offs involving timing and area constraints, reducing process complexity while maintaining optimization effectiveness
Solution Approach 2:
The system introduces an intermediary power estimation module that acts as a mediator between the memory mapping configuration and the constraint validation process. This intermediary automatically evaluates power consumption and guides the optimization process, simplifying the overall complexity by providing a systematic approach to balancing power, timing, and area constraints
3Quantity of substance
If embedded memory blocks are used to implement logical memories, then bulk data storage capability improves, but power consumption increases due to clock-driven operations
Solution Approach 1:
The system segments the embedded memory blocks into smaller sub-blocks or partitions, allowing selective activation of only those memory segments that are currently needed for data storage operations. This segmentation enables the system to maintain adequate storage capacity while reducing power consumption by keeping inactive segments in a low-power state, thus resolving the contradiction between storage capacity and power usage
Data Source
AI summary
Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.