Power-Aware Scan Partitioning for VLSI Circuit Testing

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Solution Overview

Problem

Existing scan-based testing methods for VLSI circuits face challenges in minimizing power consumption and preventing local hot spots, which can lead to false failures or permanent damage, due to uneven power distribution and the assumption that all scan chains are active at once.

Innovation Solution

A power-aware methodology for selecting and arranging scan chains by calculating power scores for each circuit cell, assigning cells to scan groups based on these scores, and ordering them to distribute power consumption evenly across the circuit, thereby avoiding localization of hot spots and adjusting scan chains to meet power budgets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If scan chains are designed to minimize scan length and wire length, then power consumption during testing is reduced, but localized hot spots may develop within the circuit

Engineering Contradiction:
Improvepower consumptionVSAvoidlocalized hot spots
Core Design Contradiction:
Loss of energyVSObject-affected harmful factors

Solution Approach 1:

The circuit is divided into multiple scan chains instead of using a single scan chain, which distributes the power consumption across multiple separate paths. This segmentation prevents concentration of power transitions in one location, thereby reducing localized hot spots while maintaining acceptable total power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different scan chains are strategically assigned to different regions of the circuit based on power consumption characteristics. High-power scan chains are distributed to different physical locations rather than concentrated in one area, creating non-uniform power distribution that avoids localized hot spots while still achieving overall power reduction through minimized scan lengths.

Inventive Principle:
Principle #3Local quality

2Device complexity

If all scan chains are assumed to be active at one time for power estimation, then power budget assessment is simplified, but the estimation may be overly conservative and exceed actual power requirements

Engineering Contradiction:
Improvepower estimation complexityVSAvoidpower budget
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

Power scores are calculated for each circuit cell in advance, before actual testing, based on cell characteristics such as driving strength and size. This preliminary power characterization allows for more accurate power estimation by considering actual cell properties rather than assuming all cells are active, enabling better power budget planning without excessive conservatism.

Inventive Principle:
Principle #10Preliminary action

3Loss of energy

If scan chains are shifted to adjust power budget, then power consumption can be reduced, but the adjustment may be inadequate and hot spots may still develop

Engineering Contradiction:
Improvepower consumptionVSAvoidhot spot prevention
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The invention changes the fundamental parameter of scan chain organization from simple shifting to power-aware assignment based on calculated power scores. By assigning scan chains to scan groups according to their power characteristics and physical locations, the system achieves more effective power control and hot spot prevention compared to mere shifting, as it considers both power consumption and spatial distribution.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11386253B2Power-aware scan partitioning
Publication Date: 2022.07.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11386253B2 patent drawing
  • US11386253B2 patent drawing
  • US11386253B2 patent drawing

AI summary

Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.