Semiconductor Package Power Bump Layout for Lower IR-Drop
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Solution Overview
Problem
The challenge is to improve power integrity in integrated circuit chips and semiconductor packages due to the reduction in the number of power bumps, which leads to IR-drop violations as the number of signal bumps increases, necessitating optimized bump placement and redistribution for effective power supply and distribution.
Innovation Solution
The solution involves arranging power bumps in a staggered fishbone shape on the integrated circuit chip, with first and second power bumps disposed along diagonal directions, and connected to metal wirings that overlap them, ensuring efficient power distribution and application of different voltages through specific metal wiring configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of signal bumps is increased to meet signal transmission requirements, then signal transmission capability is improved, but the number of power bumps that can be placed on the chip decreases, leading to power integrity deterioration
Solution Approach 1:
The power bump array is segmented into multiple groups (first power bumps and second power bumps) with different orientations. The first power bumps extend in a first direction while the second power bumps extend in a second direction, creating a staggered fishbone pattern that distributes power delivery across multiple segmented pathways, thereby improving power integrity while accommodating increased signal bumps.
Solution Approach 2:
The power bump arrangement transitions from a single-direction linear array to a two-dimensional staggered fishbone pattern. By extending power bumps in multiple directions (first direction and second direction) from a central region, the design adds dimensional complexity to the power delivery network, increasing the effective number of power bumps and their connectivity without increasing the overall chip area.
2Quantity of substance
If the number of power bumps is reduced to accommodate more signal bumps, then signal bump density is improved, but IR-drop violations occur due to insufficient power delivery
Solution Approach 1:
The power bumps are strategically positioned in a central region of the chip with specific local arrangements. The first power bumps are disposed along a first line extending in a first direction, while the second power bumps are disposed along a second line extending in a second direction, creating localized power delivery zones that optimize current distribution and reduce IR-drop in critical areas.
Solution Approach 2:
The power bump configuration uses asymmetric staggered arrangement where the first power bumps and second power bumps are offset from each other in different directions. This asymmetric fishbone pattern creates more efficient current pathways and distributes the power delivery load asymmetrically across the chip, reducing hotspots and IR-drop violations while maintaining high signal bump density.
Data Source
AI summary
An integrated circuit chip includes a substrate on which a standard cell is disposed. The integrated circuit chip includes a plurality of power bumps including a plurality of first power bumps and a plurality of second power bumps, the plurality of power bumps. disposed to have a staggered arrangement in a central region of one surface of the integrated circuit chip, and connected to provide power to the standard cell; a first metal wiring disposed below the plurality of first power bumps and electrically connected to the plurality of first power bumps, at least a part of the first metal wiring overlapping the plurality of first power bumps from a plan view; and a second metal wiring horizontally separated from the first metal wiring, disposed below the plurality of second power bumps, and electrically connected to the plurality of second power bumps, at least a part of the second metal wiring overlapping the plurality of second power bumps from the plan view. The plurality of first power bumps are disposed along a first line extending in a first direction parallel to a first diagonal direction of the integrated circuit chip, and along a second line extending in a second direction parallel to a second diagonal direction of the integrated circuit chip different from the first diagonal direction, the first diagonal direction and second diagonal direction being diagonal with respect to edges of the integrated circuit chip, and the plurality of second power bumps are disposed along a third line spaced apart from the first line and extending in the first direction, and along a fourth line spaced apart from the second line and extending in the second direction.