Power Bus Pad Assembly for Stacked Semiconductor Yield
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Solution Overview
Problem
Die stacking in semiconductor technology often results in circuit malfunctions and current leakage due to defective dies, leading to reduced product yield as entire stacks are scrapped when a single die is defective.
Innovation Solution
A semiconductor structure with a power bus and pad assemblies featuring specific gap widths allows for targeted cutting of the power bus at designated gaps to isolate defective dies, preventing electric leakage and enabling the use of otherwise functional dies in stacked semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple dies are stacked together to form an integrated component, then higher performance is achieved, but the risk of circuit defects and current leakage increases, leading to die failure and reduced product yield
Solution Approach 1:
The power bus is segmented into multiple isolated power supply regions through power isolation gaps, allowing defective dies to be electrically isolated from functional dies while maintaining power supply to healthy components. This segmentation enables the stack to continue operating with reduced functionality rather than complete failure.
Solution Approach 2:
Power isolation gaps serve as intermediary structures between adjacent dies, providing electrical isolation while maintaining mechanical stacking. These gaps act as mediators that prevent current leakage from defective dies from affecting the entire stack, allowing selective power isolation.
2Ease of manufacture
If a defective die is incorporated in the stacked dies, then the stack can be assembled, but the stack may malfunction or experience current leakage, causing die failure and deteriorating final product yield
Solution Approach 1:
Power isolation gaps are pre-designed and pre-positioned in the power bus structure before die stacking. This preliminary arrangement enables rapid identification and isolation of defective dies during assembly without requiring complex real-time diagnostics or modifications to the stacking process.
Solution Approach 2:
The defective die is electrically extracted from the functional stack through power isolation gaps that disconnect the power supply to the defective component. This extraction allows the defective die to be isolated and removed from the electrical circuit while maintaining the mechanical stack integrity and continuing operation of functional dies.
3Reliability
If the entire stack is scrapped due to one defective die, then product quality is maintained, but product yield deteriorates significantly
Solution Approach 1:
The power isolation structure enables different quality states in different regions of the stack. Functional dies maintain full power supply and operation, while defective dies are isolated with no power supply. This local quality differentiation allows the stack to deliver partial functionality rather than complete failure, improving overall yield.
Solution Approach 2:
The system discards only the defective die by isolating it through power isolation gaps, while recovering and continuing to utilize the functional dies in the stack. This selective discarding and recovery approach maximizes the usable output from each stacked component set, significantly improving product yield compared to scrapping entire stacks.
Data Source
AI summary
A semiconductor structure, a memory device, a semiconductor device and a semiconductor device manufacturing method are provided. The semiconductor structure includes a die, a power bus and a first pad assembly. The power bus is disposed on the die and extends in a predetermined direction. The first pad assembly is arranged on one side of the power bus. The first pad assembly includes at least four pads separated from one another along the predetermined direction by the first, the second and the third gaps. The first gap and the second gap both have a width larger than a width of the third gap and the first pad assembly includes a power pad coupled to the power bus and located between the first gap and the second gap. The power pad and the first and second gaps are all located between opposing ends of the power bus.