Power Cable Thick Insulation Triple Extrusion
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Solution Overview
Problem
The manufacturing of power cables with thick insulation layers faces challenges such as long vulcanization and cooling processes, longitudinal stresses, difficulty in cable centering, and limited availability of suitable cable lines, which are exacerbated by the potential for contamination and voids between multiple extruded insulation layers in existing multiple-step processes.
Innovation Solution
A method involving a power cable manufacturing process with two triple extrusion passes, where intermediate semiconductor layers of high conductivity or permittivity act as barriers to encapsulate contamination and reduce stress, allowing for the construction of cables with a total insulation thickness of 9 mm or more using existing equipment, thereby minimizing contamination and voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thick insulation layer is extruded in a single step, then manufacturing simplicity is maintained, but vulcanization and cooling times increase significantly
Solution Approach 1:
The insulation layer is divided into multiple thinner layers that are extruded in sequence, each layer being sufficiently thin to allow rapid vulcanization and cooling. This segmentation enables the manufacturing process to maintain simplicity while dramatically reducing cycle times compared to extruding a single thick layer.
Solution Approach 2:
The multiple insulation layers are extruded in rapid succession without interrupting the manufacturing process. The continuous extrusion of thin layers allows the cable to move continuously through the vulcanization and cooling zones, maintaining high productivity while reducing total processing time.
2Loss of time
If the insulation layer is extruded in multiple steps without an intermediate layer, then crosslinking and degassing times are reduced, but contamination and voids may be introduced between layers
Solution Approach 1:
A semiconducting layer is introduced as an intermediary between the multiple insulation layers. This intermediate layer serves multiple functions: it prevents contamination and void formation at the interfaces between insulation layers, maintains electrical field distribution, and allows each insulation layer to be sufficiently thin for rapid crosslinking and degassing.
Solution Approach 2:
The cable structure employs a composite design with alternating layers of insulation material and semiconducting material. This composite structure combines the electrical insulation properties of the insulation layers with the field-grading and contamination-prevention properties of the semiconducting layers, achieving both reduced processing time and high reliability.
3Productivity
If multiple extrusion layers are used in a single pass process, then equipment complexity increases, but manufacturing efficiency may improve
Solution Approach 1:
The insulation extrusion process is segmented into multiple sequential passes, each using a single extruder. This approach avoids the need for complex multi-extruder equipment while achieving the productivity benefits of multiple thin layers. Each pass extrudes one insulation layer and its associated semiconducting layers, simplifying equipment requirements.
Solution Approach 2:
The manufacturing process uses periodic repetition of the triple-extrusion sequence (insulation layer followed by two semiconducting layers) to build up the total insulation thickness. This periodic action allows standard equipment to achieve high productivity through multiple controlled passes rather than requiring complex simultaneous multi-extrusion capability.
4Reliability
If thick insulation layers are used, then cable reliability for high-voltage service is improved, but longitudinal stresses cause shrink-back of the conductor
Solution Approach 1:
The total insulation thickness is achieved through multiple thin layers rather than a single thick layer. Each thin layer undergoes controlled vulcanization and cooling with minimal thermal gradient, reducing longitudinal stresses. This prevents shrink-back of the conductor while achieving the required total insulation thickness for high-voltage reliability.
Solution Approach 2:
The process controls temperature parameters during vulcanization and cooling of each thin insulation layer to minimize thermal gradients and associated longitudinal stresses. By maintaining appropriate temperature profiles and cooling rates, the patent prevents conductor shrink-back while achieving complete crosslinking of the insulation layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases manufacturing efficiency by reducing curing and cooling times, minimizing shrink-back and sag, and enabling the production of high-voltage cables with improved reliability and flexibility, while utilizing existing equipment and potentially different insulation types for inner and outer layers.
Implementation Method 1
intermediate semiconductor layers of high conductivity or permittivity act as barriers to encapsulate contamination and reduce stress
Implementation Method 2
Extruding about the conductor a first insulation layer positioned between first and second semiconductor layers
Implementation Method 3
sufficiently long vulcanization processes to ensure adequate crosslinking of the inner layers of the insulation
Implementation Method 4
sufficient cooling process to cool the cable to enable reeling
Implementation Method 5
long degassing times required to remove crosslinking byproducts via a diffusion process through thick layers of insulation
Data Source
Figure 1~3
Figure 4~5
AI summary
A power cable comprising a: (A) Conductor, (B) First semiconductor in contact with the conductor; (C) First insulation layer in contact with the first semiconductor; (D) Second semiconductor layer in contact with the first insulation layer; (E) Third semiconductor layer in contact with the second semiconductor layer; (F) Second insulation layer in contact with the third semiconductor layer; and (G) Fourth semiconductor layer in contact with the second insulation layer.