Power Device Cell Layout for Electrical Isolation and Heat Dissipation
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Solution Overview
Problem
High voltage power semiconductor devices require electrical insulation between the backside of the device and the heat sink, but standard PCB laminates have low thermal conductivity, limiting thermal dissipation and increasing costs when using higher thermal conductivity laminates.
Innovation Solution
A power device cell design featuring a metallic body with a vertical power semiconductor die and an organic and/or glass electrical insulator confined to the metallic body, providing electrical insulation and allowing for improved thermal dissipation without the need for additional laminate layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard laminate layer is introduced to electrically isolate the backside of the power device cell from the PCB metallization, then electrical insulation is achieved, but thermal conductivity is low (∼0.65 W/K) which limits thermal dissipation
Solution Approach 1:
The electrical insulation is segmented to be applied only in specific areas where electrical isolation is required, rather than using a continuous laminate layer across the entire backside. This allows thermal paths to remain open in areas where insulation is not needed.
Solution Approach 2:
Electrical insulation is applied locally only to specific regions of the backside where electrical isolation from PCB metallization is required, rather than uniformly across the entire surface. This localized approach maintains thermal conductivity in areas where insulation is not necessary.
2Temperature
If a high thermal conductivity laminate is used to improve thermal dissipation, then thermal performance is improved, but the cost increases significantly
Solution Approach 1:
Instead of applying expensive high-thermal-conductivity laminate material across the entire backside area, the solution uses standard laminate material only in the specific partial areas where electrical insulation is required, achieving sufficient thermal management without excessive material cost.
Solution Approach 2:
The patent uses standard, lower-cost laminate material for electrical insulation rather than expensive high-thermal-conductivity laminate, accepting that the insulation layer will be thin and localized, thereby reducing overall material costs while maintaining functional performance.
3Temperature
If drilling vias through the laminate for thermal management is performed, then thermal dissipation is improved, but cost increases due to both laminate material cost and drilling/filling operations
Solution Approach 1:
The patent extracts the electrical insulation function from the thermal management function, allowing thermal vias to be implemented without requiring expensive high-thermal-conductivity laminate material across the entire structure. The insulation is taken out as a separate, localized feature.
Solution Approach 2:
The backside structure is segmented into areas requiring electrical insulation and areas requiring thermal conduction, allowing different material and processing approaches to be applied to each segment, thereby reducing overall manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves low-cost, high-performance electrical insulation and enhanced thermal dissipation, reducing the need for expensive high-thermal-conductivity laminates and minimizing the cost of drilling vias for thermal management.
Implementation Method 1
an organic and/or glass electrical insulator covering the second main surface of the metallic body such that the power device cell is electrically insulated
Implementation Method 2
the metallic body is at the same electric potential as the backside of the vertical power semiconductor die
Data Source
AI summary
A power device cell includes: a metallic body having a first main surface, a second main surface opposite the first main surface, and a side face vertically extending between the first and second main surfaces; a vertical power semiconductor die in a recess formed in the first main surface of the metallic body; and an organic and/or glass electrical insulator covering the second main surface of the metallic body such that the power device cell is electrically insulated at least at a first side that includes the organic and/or glass electrical insulator. The organic and/or glass electrical insulator is confined to the metallic body. A backside of the vertical power semiconductor die is configured to be at a different electric potential than a frontside of the vertical power semiconductor die. The metallic body is at the same electric potential as the backside of the vertical power semiconductor die.