Power Chip Alternating Switches Reduce Parasitic Inductance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-frequency low-voltage Buck circuits in data centers face efficiency bottlenecks due to parasitic inductance in commutation circuits, which increases power switch losses and voltage spikes, making it difficult to achieve high power density and efficiency simultaneously.
Innovation Solution
A power chip design with alternately arranged first and second power switches and a metal region with stacked layers, reducing the geometrical center distance between switches and capacitors, thereby minimizing parasitic inductance and improving efficiency by optimizing the commutation circuit area and conduction loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processing capacity per unit volume of server is increased by increasing the number and integration level of processing chips, then the data processing capacity is improved, but the occupied space and power consumption are increased
Solution Approach 1:
The patent changes the physical parameters of the power supply system by reducing the area of metal electrodes and optimizing their layout. This reduces parasitic inductance and enables higher switching frequencies, allowing the power supply to achieve higher efficiency and power density without proportionally increasing power consumption, thus resolving the contradiction between processing capacity and power consumption
2Power
If the area of metal electrodes in the metal region is increased, then the current carrying capacity is improved, but the parasitic inductance is increased
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. Multiple metal electrode layers are stacked vertically with alternating connection relationships, allowing current to flow through multiple parallel paths in the vertical dimension. This reduces parasitic inductance while maintaining current carrying capacity, as the effective area is increased through the third dimension rather than expanding horizontally
3Power
If the switching frequency of power switches is increased to improve power density, then the power density is improved, but the power switch losses and voltage spikes are increased
Solution Approach 1:
The patent changes the geometric parameters of metal electrodes (reducing area) and their spatial arrangement (alternating stacked layout). This reduces parasitic inductance, which allows higher switching frequencies to be used without excessive voltage spikes and switching losses. The reduced parasitic inductance enables the system to achieve higher power density while maintaining acceptable loss levels
Data Source
AI summary
A power chip includes: a first power switch, formed in a wafer region and having a first and a second metal electrodes; a second power switch, formed in the wafer region and having a third and a fourth metal electrodes, wherein the first and second power switches respectively constitute an upper bridge arm and a lower bridge arm of a bridge circuit, and the first and second power switches are alternately arranged; and a metal region, at least including a first metal layer and a second metal layer that are stacked, each metal layer including a first to a third electrodes, and electrodes with the same voltage potential in the metal layers are electrically coupled.