Power Chip Packaging Structure for Copper Wire Bonding Stress
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Solution Overview
Problem
The transition from aluminum wire bonding to copper wire bonding in power chip packaging structures poses a higher risk of damage due to increased mechanical strength and higher wire bonding energy, necessitating a new approach to manage stress distribution.
Innovation Solution
A power chip packaging structure is designed with a ceramic substrate, multiple copper layers, and specific arrangements of copper layers and wires to distribute stress effectively, using thicker second copper layers to absorb and distribute wire bonding stress, thereby protecting the power chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper wire is used instead of aluminum wire for better electrical and thermal conductivity, then electrical conductivity and thermal conductivity are improved, but wire bonding energy increases and mechanical strength increases causing higher damage risk to power chip
Solution Approach 1:
The copper layer on the contact pad is divided into multiple segments: a first copper layer directly on the contact pad, and multiple second copper layers formed on the first copper layer. This segmentation allows the stress from wire bonding to be distributed across multiple layers and regions, reducing the concentration of stress at any single point and thereby protecting the power chip from damage while maintaining excellent electrical and thermal conductivity.
Solution Approach 2:
The invention transitions from a single-layer copper structure to a multi-layer copper structure by adding vertical dimensionality. The first copper layer and multiple second copper layers are formed at different heights/thicknesses, creating a three-dimensional stress distribution system that effectively manages the high mechanical strength and bonding energy of copper wires.
2Reliability
If copper wire bonding is applied with higher mechanical strength, then electrical conductivity is improved, but stress concentration increases causing potential chip damage
Solution Approach 1:
Different regions of the copper layer structure are assigned different functions and properties. The first copper layer provides a broad stress-distribution base, while the second copper layers (with thickness ratio of 2:1 to 10:1 compared to the first layer) provide localized stress absorption points. The peripheral region of the first copper layer extends beyond the second copper layers to further distribute stress, creating a hierarchical quality distribution that optimizes both conductivity and stress management.
Data Source
AI summary
A power chip packaging structure includes: a ceramic substrate; a first and a second top metal layers are formed on the ceramic substrate; a bottom metal layer formed on the ceramic substrate; a power chip having an active surface and a chip back surface. The active surface has a contact pad, and the chip back surface is connected to the first top metal layer. One or more first copper layers are formed on the contact pad, a top surface of the first copper layer has a peripheral region and an arrangement region surrounded by the peripheral region. Multiple second copper layers are formed in the arrangement region and separated from each other. Each of multiple wires is respectively connected to the second copper layer with one end and connected to the second top metal layer with the other end.