Power Management Chip Mode Switching for Low-Leakage Soft Start
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Solution Overview
Problem
Power management chips face challenges in reducing leakage current in LDO mode and overshoot in buck mode, particularly during start-up and mode transitions, which affect the stability and accuracy of output voltage.
Innovation Solution
A power management chip design that includes a first and second power switch, error amplifiers, pulse width modulation logic, gate drivers, multiplexers, inductor detection logic, and a comparator to detect the presence of an inductor and switch between LDO and buck modes, using a sleep LDO for soft-start-up and short-circuiting the inductor both end switch to prevent overshoot.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a power management chip operates in LDO mode, then the output voltage is simple to control, but leakage current increases
Solution Approach 1:
The sleep LDO circuit performs preliminary voltage establishment before the main LDO operates. By pre-charging the output capacitor and establishing the output voltage to within 10% of the target value, the main LDO's leakage current impact is minimized, allowing the chip to achieve both easy voltage control and reduced leakage current in LDO mode.
2Loss of energy
If a power management chip operates in buck mode, then power conversion efficiency is improved, but output voltage overshoot occurs during mode transitions
Solution Approach 1:
The sleep LDO circuit performs preliminary voltage establishment before the buck converter takes over. By pre-charging the output capacitor and establishing the output voltage to within 10% of the target value, the buck converter starts from a controlled initial state, significantly reducing output voltage overshoot during mode transitions while maintaining high power conversion efficiency.
Solution Approach 2:
The sleep LDO acts as a cushioning mechanism during mode transitions. It absorbs the initial power surge and voltage spike that would otherwise occur when the buck converter starts up, providing a smooth transition and protecting the output voltage from excessive overshoot.
3Device complexity
If a power management chip uses a single circuit for both LDO and buck modes, then device complexity is reduced, but leakage current in LDO mode increases
Solution Approach 1:
The power management chip is segmented into two distinct operational circuits: a sleep LDO circuit for preliminary voltage establishment and a main LDO or buck circuit for final voltage regulation. This segmentation allows the sleep LDO to handle the high-current startup phase without affecting the low-leakage performance of the main LDO during steady-state operation, thus reducing overall leakage current while maintaining relatively simple device complexity.
Data Source
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AI summary
A power management chip includes a gate driver configured to output a first gate signal driving a first power switch and a second gate signal driving the second power switch, a multiplexer configured to receive an error detect signal from a first error amplifier and a first gate signal from the gate driver, and drive the first power switch with either of the error detect signal or the first gate signal in response to a mode select signal; an inductor detection logic configured to receive the inductor detect signal, output a comparison detect signal and a pulse signal for detecting an external inductor, and output the mode select signal corresponding to a result of the detecting, and a comparator comparing an internal output voltage of an output node and an output voltage of the feedback node in response to the comparison detect signal.