Power Chip Packaging Structure With Direct Soldered Frame Connections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing circuit board packaging structures with power chips experience high parasitic inductance and significant power loss during high-speed switching due to conventional wire connections, which need improvement.
Innovation Solution
The solution involves connecting power chip electrodes directly to frames via soldering, forming a packaging structure with a copper-cladding substrate and multilayer circuit board, and using conductive posts to reduce parasitic inductance and improve electrical connections, thereby reducing power loss and increasing switching frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire connections (gold wires or aluminum wires) are used to connect power chip electrodes to frames, then electrical connection is achieved, but parasitic inductance increases and power loss occurs during high-speed switching
Solution Approach 1:
The patent removes the wire connections (gold wires or aluminum wires) from the electrical connection path between power chip electrodes and frames. By extracting this intermediate connection element, the patent eliminates the parasitic inductance and power loss associated with wire connections, achieving direct electrical connection through soldering.
Solution Approach 2:
The patent merges the power chip electrodes directly with the frames through soldering, eliminating the separate wire connection component. This merging of previously separate elements (power chip and frame) into a direct connection reduces the number of interfaces and minimizes parasitic inductance, thereby reducing power loss during high-speed switching.
2Reliability
If wire connections are used to connect power chip to frames, then electrical connection is established, but parasitic inductance is high
Solution Approach 1:
The patent extracts and removes the wire connections from the electrical path, eliminating the source of parasitic inductance. By taking out this intermediate connection element, the patent achieves direct soldering connection between power chip electrodes and frames, significantly reducing parasitic inductance while maintaining electrical connection reliability.
3Ease of manufacture
If conventional packaging structure with wire connections is used, then manufacturing process is simple, but power loss is significant during high-speed switching
Solution Approach 1:
The patent changes the connection method parameter from wire bonding to direct soldering. This parameter change in the manufacturing process eliminates the wire connection step while establishing a direct metallurgical bond between power chip electrodes and frames, thereby eliminating parasitic inductance and reducing power loss during high-speed switching operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic inductance and power loss, enhances connection reliability, and increases power density and switching frequency by optimizing electrical connections and heat dissipation in the circuit board module.
Implementation Method 1
connecting power chip electrodes directly to frames via soldering
Implementation Method 2
copper-cladding substrate and multilayer circuit board, and using conductive posts to reduce parasitic inductance
Implementation Method 3
the frame having the power chip is subjected to injection molding to form a packaging assembly
Data Source
AI summary
A packaging structure and a circuit board having the packaging structure are provided. The packaging structure includes a power chip, a wire, a grid terminal, a first soldering layer, a second soldering layer, a first frame, a second frame, and a packaging body. The power chip has a grid electrode, a source electrode, and a drain electrode. The grid terminal is connected to the grid electrode through the wire. The first frame is connected to the source electrode through the first soldering layer. The second frame is connected to the drain electrode through the second soldering layer. The packaging body covers the power chip, the grid terminal, the first frame, the second frame, the wire, the first soldering layer and the second soldering layer.