Power Circuit Package Using Membrane Structure for Cost Reduction
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Solution Overview
Problem
High power semiconductor modules packaged with brazed or direct bond copper to ceramic substrates are expensive and limited to high-performance applications, with existing cost-saving and reliability improvements being insufficient.
Innovation Solution
A power circuit package comprising a substrate with interconnect circuit layers and via connections, coupled with a power semiconductor module attached to a membrane structure, allowing for efficient thermal and electrical interconnects and integration of surface mount components, using materials like insulated metal substrates and polymer-based membrane structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If brazed or direct bond copper to ceramic substrates is used for packaging high power semiconductor modules, then high performance and reliability are achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent changes the material parameters of the substrate from expensive ceramic to cost-reduced materials such as printed circuit boards or insulated metal substrates, while maintaining the functional requirements for electrical insulation and mechanical support. This parameter substitution resolves the contradiction by achieving acceptable reliability at lower cost.
Solution Approach 2:
The patent employs cheaper substrate materials that can be mass-produced using standard PCB or metal substrate fabrication techniques, replacing the expensive ceramic substrates that require specialized brazing processes. This approach accepts reduced material longevity in exchange for significant cost reduction and improved manufacturability.
2Reliability
If ceramic substrates with copper bonding are used, then high performance applications are supported, but application scope is limited
Solution Approach 1:
The patent designs a universal packaging structure that can accommodate different power semiconductor modules using standard substrate materials. The interconnect structure and membrane assembly are configured to work with various device types, enabling the same packaging platform to serve multiple applications from automotive to industrial to consumer electronics, thus expanding adaptability while maintaining performance.
3Ease of manufacture
If traditional wire bonding is used for interconnects, then electrical connections are established, but reliability and cost-effectiveness are insufficient
Solution Approach 1:
The patent extracts the wire bonding process entirely from the interconnect structure and replaces it with direct membrane-to-device pad bonding. This eliminates the intermediate wire bond step that introduces reliability concerns and additional cost, achieving both improved reliability and cost reduction simultaneously.
Solution Approach 2:
The patent merges the electrical interconnect function and mechanical support function into a single integrated membrane structure that bonds directly to the device pads. This consolidation eliminates separate wire bonds and reduces the number of interconnect interfaces, thereby improving reliability while reducing manufacturing complexity and cost.
Data Source
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AI summary
A power circuit package (10) includes a base (12) including a substrate (14), a plurality of interconnect circuit layers (16) over the substrate with each including a substrate insulating layer (18) patterned with substrate electrical interconnects (20), and via connections (22, 24) extending from a top surface of the substrate to at least one of the substrate electrical interconnects (20); and a power semiconductor module (26) including power semiconductor devices (28) each including device pads (30) on a top surface of the respective power semiconductor device and backside contacts (31) on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure (32), the membrane structure including a membrane insulating layer (34) and membrane electrical interconnects (36) over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts (31) are coupled to selected substrate electrical interconnects or via connections.