Power Clamp Circuit Shared Discharge Path ESD EOS Protection
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Solution Overview
Problem
Existing integrated circuit designs face challenges in simultaneously achieving Electrical Static Discharge (ESD) and Electrical Overstress (EOS) protection, leading to increased chip area occupation and leakage current, which reduces the standby time of mobile devices.
Innovation Solution
A power clamp circuit and dual-clamp method that utilize a single discharge path for both ESD and EOS protection, incorporating an EOS protection module, ESD protection module, and a switch control module to monitor power supply voltage and trigger appropriate discharge paths for overload and electrostatic events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clamp circuits are used for ESD protection and EOS protection, then both protection functions can be achieved, but chip area occupation increases and leakage current increases
Solution Approach 1:
The patent combines ESD protection and EOS protection into a single shared clamp circuit. The first clamp unit (for ESD) and second clamp unit (for EOS) share common connection nodes and discharge paths, merging two separate protection functions into one integrated circuit structure, thereby reducing chip area occupation while maintaining both protection capabilities
Solution Approach 2:
The shared clamp circuit is designed to perform multiple functions: it can discharge ESD currents through the first clamp unit, discharge EOS currents through the second clamp unit, and both units share common power supply connections and ground references. This multi-functional design allows a single circuit structure to provide both ESD and EOS protection
2Reliability
If separate clamp circuits are used for ESD protection and EOS protection, then both protection functions can be achieved, but leakage current increases and standby time decreases
Solution Approach 1:
By merging the ESD and EOS clamp circuits into a shared structure with common connection nodes, the patent reduces the total number of discrete components and interconnections. This consolidation decreases the cumulative leakage current from multiple separate circuits while maintaining both protection functions through the unified clamp architecture
3Temperature
If NMOS bigFETs with large width are used to reduce current density, then temperature rise is reduced, but chip area occupation increases
Solution Approach 1:
The patent segments the protection function into two specialized clamp units: the first clamp unit handles ESD protection with optimized transistor sizing for high-voltage transient events, and the second clamp unit handles EOS protection with transistor sizing optimized for sustained overload conditions. This segmentation allows each unit to use appropriately sized transistors for its specific function rather than requiring all units to use oversized transistors, thereby reducing total chip area while managing temperature rise through functional specialization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively combines ESD and EOS protection, reducing chip area usage and leakage current, thereby increasing the standby time of integrated circuits by using a shared discharge path controlled by detection and control units within the power clamp circuit.
Implementation Method 1
turning on the discharge path based on the EOS protection signal to discharge an overload current, and turning on the discharge path based on the ESD protection signal to discharge an electrostatic current
Data Source
AI summary
The present disclosure provides a power clamp circuit, a chip, and a dual-clamp method. The power clamp circuit is applied to a circuit system to monitor the power supply voltage of the circuit system and includes: an EOS protection module, for outputting an EOS protection triggering signal when it is determined that the circuit system is electrically overstressed based on the power supply voltage; an ESD protection module, for outputting an ESD protection triggering signal when it is determined that an electrostatic event is present in the circuit system based on the power supply voltage; a switch control module, for turning on a discharge path based on the EOS protection signal to discharge an EOS current, and turning on the discharge path based on the ESD protection signal to discharge an electrostatic current.