Switching Power Clock Synchronization Without Extra Mode Pins

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving synchronization among multiple devices, particularly in switching power devices where efficient voltage regulation and phase synchronization are crucial.

Innovation Solution

The proposed solution involves a switching power device configuration with two power supply control devices operating in different modes. One device operates in a first mode synchronized with a reference clock signal, while the other operates in a second mode synchronized with an input clock signal. This configuration allows for efficient voltage regulation and phase synchronization without the need for additional external terminals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a dedicated external terminal is added for mode setting, then the device can flexibly switch between synchronization modes, but the device size and complexity increase

Engineering Contradiction:
Improvemode switching capabilityVSAvoidterminal quantity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The synchronous input terminal and synchronous output terminal are designed to serve dual purposes: they function as synchronization signal interfaces and simultaneously as mode setting terminals. By detecting the presence or state of signals at these existing terminals, the device determines whether to operate in master mode or slave mode, thereby eliminating the need for dedicated mode setting terminals while maintaining flexible mode switching capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the mode setting function with the existing synchronization signal transmission function. The mode determination is performed by detecting the state of the synchronous output terminal signal, which merges the configuration function into the existing synchronization interface, reducing the total number of terminals required

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If multiple external terminals are used for synchronization control, then precise synchronization can be achieved, but manufacturing cost increases

Engineering Contradiction:
Improvesynchronization precisionVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The synchronous output terminal serves multiple functions: it outputs the reference clock signal for synchronization, and simultaneously acts as a mode setting terminal whose signal state determines whether the device operates in master or slave mode. This multi-functionality reduces the need for additional terminals, lowering manufacturing complexity and cost while maintaining precise synchronization capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The device automatically determines its operating mode by detecting the state of the synchronous output terminal signal without requiring external mode setting terminals or additional configuration components. This self-determination mechanism eliminates the need for extra terminals and simplifies the manufacturing process while ensuring reliable synchronization

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250038669A1Semiconductor Device, Semiconductor System and Switching Power Device
Publication Date: 2025.01.30 ROHM CO LTD
  • US20250038669A1 patent drawing
  • US20250038669A1 patent drawing
  • US20250038669A1 patent drawing

AI summary

The present disclosure provides a semiconductor device, including: a synchronous input terminal; a synchronous output terminal; a functional circuit, having a reference clock signal generating circuit operable to generate a reference clock signal; a signal output circuit, connected to the synchronous output terminal; and a mode setting circuit, for setting an operation mode of the functional circuit and the signal output circuit to a first mode or a second mode through a mode determination process. The functional circuit is operable to perform a predetermined functional operation in synchronization with the reference clock signal in the first mode, and perform the functional operation in synchronization with an input clock signal transmitted to the synchronous input terminal from another semiconductor device in the second mode. The signal output circuit is operable to output a clock signal based on the reference clock signal from the synchronous output terminal in the first mode.