Power-Collapsible Design-for-Test Logic for SoC Power Control
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Solution Overview
Problem
SoC designs face increased power consumption and temperature issues during testing and normal operation due to self-testing logic, which can lead to errors and inefficiencies, especially with aging circuitry and power grid inefficiencies.
Innovation Solution
Implementing power collapsible self-testing architecture with dedicated and distributed power domains, allowing self-testing logic to be disconnected during non-testing operations, reducing power consumption and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-testing logic is always active to ensure SoC quality and detect errors, then testing accuracy and reliability are improved, but power consumption increases during normal operation
Solution Approach 1:
The self-testing logic transitions from a static always-on state to a dynamic state that can be activated or deactivated based on operational needs. Power control logic dynamically manages the power supply to self-testing logic, enabling it to be collapsed (powered down) during normal operation and activated only when testing is required, thus resolving the contradiction between continuous reliability and energy consumption.
Solution Approach 2:
Instead of continuous operation, the self-testing logic is activated periodically or on-demand based on specific conditions. The system performs functional operations during normal periods and activates self-testing logic only when needed for testing phases, converting continuous power consumption into periodic, controlled activation that maintains reliability while reducing overall energy use.
2Reliability
If self-testing logic is always active to detect errors during aging and malicious attacks, then error detection capability is improved, but power drain during normal operation increases
Solution Approach 1:
The power state of self-testing logic is made dynamic rather than static. Power control logic enables the system to adapt the power supply state based on whether error detection is currently needed, allowing the self-testing logic to be deactivated during normal operation when error detection is not required, thus eliminating unnecessary power drain while maintaining detection capability when needed.
3Productivity
If self-testing architecture is added to enable quick and accurate testing, then testing functionality is improved, but power efficiency during normal operation deteriorates
Solution Approach 1:
The self-testing architecture incorporates dynamic power management where power control logic adjusts the power supply state of self-testing logic based on operational mode. During normal functional operations, the self-testing logic is powered down to maintain power efficiency. When testing is required, power is restored to enable full testing functionality, thus resolving the contradiction between having available testing functionality and maintaining power efficiency during normal operation.
Data Source
AI summary
This disclosure provides systems, methods, and devices for memory systems that support enhanced processing core scheduling schemes. In a first aspect, a system-on-a-chip (SoC) includes functional logic configured to perform one or more functions and self-testing logic configured to perform a self-testing operation on the functional logic. The SoC also includes a plurality of power domains, including a functional power domain coupled to the functional logic and configured to provide power to the functional logic and a self-testing power domain coupled to the self-testing logic and configured to provide power to the self-testing logic. The SoC further includes power control logic configured to control power delivery from the plurality of power domains to the functional logic and the self-testing logic and configured to power collapse the self-testing logic. Other aspects and features are also claimed and described.